Any plans for better design rule support?

[jilvonenJXYK7]

Hi,

Is there any plans to include support for the following features:

- proper padstack support (per layer annular rings, different microvia sizes, staggared/stacked microvias, filled/plated-over vias, backdrilled vias, ...  )

- per-layer design rules (different layers need sometimes different annular rings and hole sizes and also different trace widths and clearances to get the right impedances)

- high-speed design rules

Trying to design an 2-4-2 HDI board and it is doable but Eagle keeps fighting back quite hard.

[jorge_garcia]

Hi @jilvonenJXYK7,

I hope you're doing well. We do have plans to improve the DRC but these are currently longer term goals. There is nothing in the near term that we are working on to improve the DRC.

Please let me know if there's anything else I can do for you.

Best Regards,

[john2W58P]

Have you at least fixed the confusion between microvias and via in pad, where you can no longer (as of version 9.0 and continuing through at least 9.3.1) places micro vias in arbitrary locations? 

This is a pretty basic and fundamental bug (or confusion on the part of a developer who doesn't make circuit boards more likely) that has me and probably everyone else doing even minimally HDI stuff stuck on version 8.7. 

Not asking for anything shiny and new, just fix what ya broke!