DRC errors for top layer overlapping polygon pours to same net unless I add a trace to connect

[mjstn2011]

Here is what I have found that seems odd and I want clarity that my approach is ok below for overlapping polygon pours to the same net showing DRC error as if they are not connected and showing a single rats-next as if unconnected line.

1. Create two polygon pours that overlap on one or more edges
2. Both pours specify signal name of GND or some other unique NET name such as in a 2nd case of this where VOUT is the signal name on 2 other pours.
3. Have one pour specify use of Thermals and the other pour without Thermals.  This allows surface mount parts on the without thermals pour to connect to that pour

The specific case I use has the pour with thermals under a BGA and the connecting pours without thermals that overlap away from the BGA to allow SMT parts to connect.

I end up with a single DRC fault and unconnected airwire between these two pours unless I manually add a single trace connecting one pin of a part on each pour to a pin of a part on the other pour.

Is this expected?   Before I solved this I had made test boards where the pours overlap properly so there really is a 'connection' between the pours but the software thinks there is no connections.

Thank you for your time,   Mark Johnston

[jorge_garcia · Accepted solution]

Hello @mjstn2011 ,

I hope your doing well. This has been coming up quite a bit lately. Basically, there is an issue in the way these polygons are handled that leads to the extra airwire even though you do in fact have a continuous copper pour. I'll add this thread to the existing ticket for this issue.

So long story short you aren't doing anything wrong. It's just a bug currently.

Let me know if there's anything else I can do for you.

Best Regards,

[mjstn2011]

That you for the fast reply that clarifies this is a known issue.  I'm glad to have offered my observations so the team can work on this issue for some future release.