Spice Simulator Error (AD620)
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Hi all,
I have incorporated a Spice model from Analog Devices into a component I am using on one of my projects. The simulation seams to be executing, but then I get this error:
No. of Data Rows : 508
PPerror: syntax error
Note: No ".plot", ".print", or ".fourier" lines; no simulations run
I had to modify the model slightly from the original, in order to satisfy the Fusion pin-mapping feature. Here it is:
* non-inverting input
* | inverting input
* | | Rg1
* | | | Rg2
* | | | | positive supply
* | | | | | negative supply
* | | | | | | output
* | | | | | | | reference
* | | | | | | | |
.SUBCKT AD620 P N RG1 RG2 VSS VDD OUT REF
QIN1 VDD P A3 QPI1
QIN2 VDD N A4 QPI2
IBIAS1 VSS A3 2u
IBIAS2 VSS A4 2u
R1 RG1 103 50k
R2 RG2 104 50k
CMR RG1 VSS 0.5p
R3 104 202 50k
R4 103 201 50k
*
* Output stage common-mode error
*
R5 201 REF 50.004k
R6 202 OUT 49.996k
Icor VSS VDD 1.25e-4
*
* INPUT STAGE
*
Q1B B4 B3 B5 QPI
Q2B B6 202 b7 QPI
RC1B VDD B4 8.5k
RC2B VDD B6 8.5k
RE1B B5 B8 3.3k
RE2B B7 B8 3.3k
ENOISB 201 B3 B53 98 1
D1B B3 VSS DX
D2B VDD B3 DX
IBIASB VSS B8 10u
*
* INTERNAL VOLTAGE REFERENCE
*
EREF1 98 97 VSS 0 0.5
EREF2 97 0 VDD 0 0.5
*
* VOLTAGE NOISE STAGE
*
DN1B B51 B52 DNOI1
VN1B B51 98 0.64
VMEASB B52 98 0
RNOI1B B52 98 1
F1B B53 98 VMEASB 1
RNOI2B B53 98 1
*
* INTERMEDIATE GAIN STAGE WITH POLE = 578kHz
*
G1B 98 B20 B4 B6 1E-3
RP1B 98 B20 550
CP1B 98 B20 500p
*
* INTERMEDIATE GAIN STAGE WITH POLE = 900kHz
*
G2B 98 B21 B4 B6 1E-3
RP2B 98 B21 500
CP2B 98 B21 354p
*
* GAIN STAGE WITH DOMINANT POLE
*
G4B 98 B30 B21 98 3.65E-3
RG1B B30 98 25k
CF1B B30 OUT 0.275n
D5B B31 VSS DX
D6B VDD B32 DX
V1B B31 B30 0.6
V2B B30 B32 0.6
*
* OUTPUT STAGE
*
Q3B OUT B42 B43 QPOX
Q4B OUT B44 B46 QNOX
RO3B VSS B43 30
RO4B B46 VDD 30
VBI01B VSS B41 0.5965
VBIO2B B47 VDD 0.5965
EO3B B41 B42 98 B30 10
EO4B B44 B47 B30 98 10
*
* INPUT STAGE
*
Q1C C4 C5 C8 QPI
Q2C C6 RG1 C8 QPI
RC1C VDD C4 8.5k
RC2C VDD C6 8.5k
ENOIC A3 C5 C53 98 1
D1C C3 VSS DX
D2C VDD C3 DX
IBIASC VSS C8 10u
*
* VOLTAGE NOISE STAGE
*
DN1C C51 C52 DNOI1
VN1C C51 98 0.64
VMEASC C52 98 0
RNOI1C C52 98 1e-4
F1C C53 98 VMEASC 1
RNOI2C C53 98 1
*
* INTERMEDIATE GAIN STAGE
*
G1C 98 C20 C4 C6 1E-3
RP1C 98 C20 4.67k
*
* GAIN STAGE WITH DOMINANT POLE
*
G4C 98 C30 C20 98 2E-3
RG1C C30 98 125k
CF1C C30 103 2.5n
D5C C31 VSS DX
D6C VDD C32 DX
V1C C31 C30 0.6
V2C C30 C32 0.6
*
* OUTPUT STAGE
*
Q3C 103 C42 C43 QPOX
Q4C 103 C44 C46 QNOX
RO3C VSS C43 30
RO4C C46 VDD 30
VBI01C 99 C41 0.5965
VBIO2C C47 VDD 0.5965
EO3C C41 C42 98 C30 5
EO4C C44 C47 C30 98 5
*
* INPUT STAGE
*
Q1D D4 D5 D8 QPI
Q2D D6 RG2 D8 QPI
RC1D VDD D4 8.5k
RC2D VDD D6 8.5k
ENOID A4 D5 D53 98 1
D1D D3 VSS DX
D2D VDD D3 DX
IBIASD VSS D8 10u
*
* VOLTAGE NOISE STAGE
*
DN1D D51 D52 DNOI1
VN1D D51 98 0.64
VMEASD D52 98 0
RNOI1D D52 98 1e-4
F1D D53 98 VMEASD 1
RNOI2D D53 98 1
*
* INTERMEDIATE GAIN STAGE
*
G1D 98 D20 D4 D6 1E-3
RP1D 98 D20 4.67k
*
* GAIN STAGE WITH DOMINANT POLE
*
G4D 98 D30 D20 98 2E-3
RG1D D30 98 125k
CF1D D30 104 2.5n
D5D D31 VSS DX
D6D VDD D32 DX
V1D D31 D30 0.6
V2D D30 D32 0.6
*
* OUTPUT STAGE
*
Q3D 104 D42 D43 QPOX
Q4D 104 D44 D46 QNOX
RO3D VSS D43 30
RO4D D46 VDD 30
VBI01D VSS D41 0.5965
VBIO2D D47 VDD 0.5965
EO3D D41 D42 98 D30 5
EO4D D44 D47 D30 98 5
*
* Model sub-components
*
.MODEL QPI PNP(VAF=100)
.MODEL QNOX NPN(IS=6E-15,VAF=120,RC=50)
.MODEL QPOX PNP(IS=6E-15,BF=112,VAF=120,RC=50)
.MODEL DX D(IS=1E-16)
.MODEL DNOI1 D(AF=1.5, KF=6E-10)
.MODEL DNOI2 D(KF=1E-8)
.MODEL QPI1 PNP(VAF=100)
.MODEL QPI2 PNP(VAF=99.3)
.ENDS AD620