Hello Autodesk Community,
Hope you all are doing fine in this worldwide COVID-19 Pandemic!
I had one query regarding the restrict layer for internal layers in multi-layer PCB (>2 Layer)
For the Top & Bottom Layers in PCB, we have T-Restrict and B-Restrict with which we can block areas where copper pour should not be there, primarily the GND Layer Polygon, to be precise.
I am currently working on a 4 layer board. I wanted to know whether such restrict layers exist for the internal layers as well or not? If Yes, how do I enable these layers to use them in my design?
Solved! Go to Solution.
Solved by jorge_garcia. Go to Solution.
Hello @jorge_garcia
Thanks for the reply.
I was certainly unaware about cut-out polygons.
Using it I can meet my requirements for now.
Thanks for the suggestion! It definitely works!
I tried polygons, open fill and one with fill, played with priority layers but no joy.
One possible workaround is to place a zero width trace in an inner layer.
Not as good as a tRestrict, as some feature would be missing.
Likely the board mfg will ignore the zero width trace, as is cannot be etched.
Just stumbled on to this solution and I too would like to see a "Full restriction" option (4 Years later...)
The "zero width" un-designated trace did work, on a 6-layer PCB I did a year ago.
Has this been addressed yet? It has been many years and still no way to set up restrict layers for the two middle layers of a 4 layer board?
Hi there! Unfortunately this has not been addressed yet but we definitely do care and absolutely understand the need for this. There are some foundational obstacles for us to overcome for this to be implemented the right way.
Will keep you posted once there is more clarity on this.
Thanks for sharing your requirements, we do read and take note of all of these requests.
Hi everyone,
Thanks so much for your time on the forums. As @Pieter.Jan.Van.de.Maele mentioned, we absolutely do care. Feedback like yours help us understand product workflows more deeply and then prioritize product development effectively.
To that end, I'll reach out over DM and perhaps we can jump on a quick call to ensure I understand your requirements as well as some time for some more general Electronics feedback.
Best regards,
Melisa
I do not understand the meaning of "you do care". the issue is so critical and forcing your users to move to other competitors.
I assume "you do care" means you do care about your job, or your competitors but doesn't look like you care for your customers.
its been decades, issue was initially raised with cadsoft and then with Autodesk..
Do not "DM" to public relations types, let their laundry hang out to dry. That is the role of public forums, to highlight issues, not to sweep them under the rug.
So @csvanberg,
I think a clarification is in order. @melisa.kaner is not a "public relations type", she is one of our product managers, and as such has a lot of authority over what features get prioritized.
That's the reason she comes on the forums to figure out what out of thousands of requests we get should be implemented next.
We do care, and I know I've been reporting this request for years. However, there are viable workarounds (ie Cutout Polygons on the inner layers) so this request becomes less urgent compared to other things that don't have suitable workarounds. It's very much a balancing act.
If she or anyone else from the team reaches out, it's to try to gather information to make well-informed decisions of when and how to address feature requests. I get that @vikramemails is frustrated and for that we are sorry, but that doesn't mean we are ambivalent to his issues or any other customer's issues.
@vikramemails Let me know what you are trying to achieve and let's see if we can find a way to get you a solution right now so that you can finish your work .
Let me know if there's anything else I can do for you.
Best Regards,
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