Mill layer overlap with copper doesn't trigger DRC.

[Anonymous]

Recently nearly got bitten big on this. I use milling layers for cutouts on components, and the milling layers in the package don't generate DRC errors when they overlap signals. I had two traces that are just barely inside the mill outline and since the DRC check didn't catch it and the milling layer was visually off I completely missed it until the PCB manufacturer luckily pointed it out using the gerber files.

I'm not sure what the solution is other than to pay more attention to the milling layer, but it would be really nice if a mill too close to a signal triggered a DRC warning. I'd far rather approve a few unnecessary warnings than have to worry about this in the future. Is there a way to configure that?

[one-of-the-robs]

Traditionally (i.e. before Autodesk took over) the milling layer in Eagle was largely a non-functional after-thought. It does not interact with anything, does not affect DRC at all, etc.

This hasn't, yet, changed very much but I believe the devs are well aware that it needs to.

[C.Nicks]

What I've done in the past is copied everything from the milling layer into the dimension, especially on panelized designs. That way anywhere that was to be milled out also pushed polygon copper pours away from the milled edges.