Hi guys,
Very often, I work with 8 layers boards with several GND layers.
In order to shield signals and reduce impedance between the planes, I often place manually a lot of vias for example on a 2mm grid. It is the last step before finishing the PCB. This takes a lot of time, because I have to manually avoid all existing traces and pads.
It would be so nice to have a via stitching option in the polygons which takes a "spacing" parameter and an "avoid pads and traces (even on other layers)" option.
Is such a feature planed?
Thanks,
Victor
Solved! Go to Solution.
Solved by jorge_garcia. Go to Solution.
Solved by Pieter.Jan.Van.de.Maele. Go to Solution.
Yes this is planned.
Dear Peter,
Do you know when this feature will be able on Eagle ?
Thank in advance for your answer.
BR
Hello @jorge_garcia,
Thank you for your answer. This ULP will help me for the moment.
I hope the Via stitching/shielding will be there for my next project!
Thank you for your support.
BR
Hi, this feature would also be very useful for me as well. Usually in RF designs, you need to flood the top and bottom layers with ground pours, and finally stitch with vias heavily (5-8mm grid). It is a tedious and laborious operation and is a perfect candidate for automation.
Hi @ireshZS62Z,
I hope you're doing well. Unfortunately, there is no update for now, the ULP is the best solution available at this point in time.
Let me know if there's anything else I can do for you.
Best Regards,
I have some stitching workarounds in Eagle but I am not finding any for Fusion. Stitching a lines that are .1" apart is almost as tedious as stitching individual vias.
Is RF support even on an existing roadmap? Can you provide a link to the current roadmap so I can judge where the software is heading? I have a bunch of RF work coming up and have used Fusion for a few simple digital circuits but if I have to add another package for RF I want to know well in advance of my needs. Thank you.
Hi @colinNJB25 ,
I hope you're doing well. The same methods you used in EAGLE should work in Fusion 360 electronics, namely the ULP I mention further up this thread.
Fusion 360 does not currently post a public roadmap, but what I do know I'll share. For now, what we have is an export to Ansys for signal integrity and RF simulation. We do eventually want to incorporate more advanced RF features but outside of our partnership with Ansys and the technologies that will bring there are no immediate plans to address stitching in Fusion 360.
Hope this helps.
Best Regards,
Thank you. If the existing pattern command could do rectangles it would solve my immediate problem. It is clever enough to miss components. Creating a grid of vias on a .2" spacing that miss through holes, smd pads, and traces on any layer in a 4x5 board is very time consuming and not very tolerant of changes. In an ideal world it would be more like the pour command.
I see there is not a public road map. That is too bad, even though it was inaccurate for years the Fusion modeling roadmap really has been very helpful. I was an early adopter of Fusion and am very glad I stuck with it.
Via stitching will be released in the March release of Fusion Electronics.
You can get early access to it now as part of our insider program: https://www.autodesk.com/campaigns/fusion-360/insider-program?_ga=2.209938003.756170057.1709510369-8...
Thanks for your patience all!!
Just wanted to let you all know that via stitching is now live in the March update of Fusion Electronics: https://www.autodesk.com/products/fusion-360/blog/march-2024-product-update-whats-new/#electronics
There's quite a few other interesting features like cross highlighting, spice export, removal of unused annular rings, cross-talk for the Signal Integrity extension etc.
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