I need to make castellated edges on a daughter board.
When I draw a footprint in the library I get this satisfactory result:
When I put the part in the schematic and view the BRD I see this (which does not work):
The application is making a daughter board that will be soldered directly to a motherboard. The top layer pad, bottom layer pad and the PTH are all necessary to transfer the heat during soldering.
Can anyone tell me what's happening from the library to the board?
Solved! Go to Solution.
Solved by AutodeskEagleCad. Go to Solution.
In case someone else end up fighting this POS for 20 hours like I did, it's the % setting in Annular Ring in the DRC.
and this is the result on the BRD:
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