OK -- here is a couple example of how this affects me...daily....
1. I create a 2 layer board and add a ground and vcc polygon that matches the size of the board.
2. Autoroute it to "100%" ...
3. vcc and ground are not routed, and the polygons often become fragmented from other nets crisscrossing everywhere. OK, that's expected for a two layer board with planes and any complexity....but now I have unrouted / incomplete ground and vcc nets 😞
4. if the gaps are minor, I can manually route them, adjust via positions to maintain the copper pour continuity, etc. (it would be nice if the autorouter could position vias to avoid cutting off a copper pour unnecessarily)
HOWEVER
If I rename my polygons before autorouting, then vcc and gnd get completely routed. Often I'll route them with a pretty thin net class. Then I can switch the polygon net names back and the cooper pour fills in the spaces ( and the routed traces guarantee contiguity). Then I have a board that is really 100% routed, and has poured copper to maximize vcc and gnd coverage / heat dispersion (even if some sections are thinly connected islands, the connections are usually short)
Another, related example:
Lets say I've got some high power n channel mosfets and they need a lot of copper for high current capacity. But not every component that connects to ground is high current. Basically, not every segment of the a net needs to be the same width. But split nets aren't supported. So.....I've got a couple workarounds, with different problems:
1. I have to set the fat trace widths (ie: 15-50mil) in the net classes dialog, autoroute but select only those nets. After autorouting, I rip up all the fat traces that don't need to be fat. Then I go back and switch the net classes back to a thin width and autoroute again, this time creating thin traces for the rest of the net. If I have to rip up, I often have to start all over or (tediously) rip up selectively so I don't lose manually routed traces or the fat ones (if I could LOCK a trace to prevent rip up...)
2. Use a polygon that overlaps a thinner trace in the critical area. This option usually works best for REALLY fat traces, like 50-150mil. I can manually route them, but adding a copper pour optimizes / maximizes copper area for the trace. But then there is more to the net than just that high current section--like an LED, connection to a sense resistor, or a test pad. The autorouter refuses to route anything with polygon attached (unless I rename the polygons first, which is tedious when you have many of them on a board)
3. Split the net using a fake part like a "short" -- basically two pins in schematic and two small, touching smd pads in board. The problem then is this confuses ERC/DRC checks, the shorts need to be manually placed which creates artificial connections restrictions to autorouting. Also, I can only assign one net to a polygon pour, so this trick doesn't work with nets that need heat sinking in more than one area.
If there is a fourth way to accomplish this, I'd like to hear.
The autorouter clearly CAN route nets with polygons, it incorrectly assumes it doesn't have to.
