Via hole seems to be offset?

[puresoft]

Hi,

I'm making a small board and have a few vias to connect GND from top to bottom side. I find that for one via (and also when trying to add additional vias now) I now seem to have the central hole to be offset from the copper rings?

See attached pic of back side of PCB with yellow box to highlight the anomaly of the via with offset hole. The previous vias in the design seem to be OK and show the daylight through them.

If someone from support can contact me I can email over the files to look at.

[yqliu]

Hello @puresoft , yes, please share your file and we can look at it.

[yqliu · Accepted solution]

This is a very strange bug. The hole on the board is correct, but the hole on the copper pour is incorrect. I didn't figure out how it happened, but I found a workaround: You can go back to 2D PCB, click "View 3D PCB with Canvas" and then click "View 3D PCB" again. Now the hole should be on the correct position.

[puresoft]

Thanks for the reply and workaround/solution to get it viewing correctly again. The only further info I can add is that I was having crashes yesterday, so restored the design from autosave backups, perhaps they had some syncing issues or it doesn't check the copper pour layer fully for consistency and that needs to be fully rebuilt when restoring from a backup?

[yqliu]

Glad to know the workaround works. I tried to rebuild the copper pour but no lucky.

The other fix I found, which might be more reliable, is to export the pcb document as brd,  open it again and save as a new document, then link this new pcb document to your electronics design. If later you see any issues with the previous workaround, you can try this method.