Thermals not rendering properly, DRC not catching violation?
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Context: In a design migrated from Eagle, I found the thermals in FE to have a different width from the EAGLE design. I realise that FE separates out the setting of the thermal width, which is a good change. During the migration, FE sets the thermal width to the same value the line width had in the respective polygon in Eagle, presumably to achieve the same thermal width. But the result is thinner than it was in Eagle. The example area is under a BGA chip (around H4 pin, named in bottom picture), with nested GND polygons (one spans the whole PCB with rank 3, the other only the BGA with rank 1).
Eagle:
FE:
The thermals on the H4 contact are much thinner than in the Eagle original.
Problem:
Then I manually adjusted FE's thermal width set in the BGA's GND polygon to visually match the width of the thermals in the Eagle design, i.e., I changed thermal width such that it results in thermals on H4 pin to be approximately same width as in EAGLE. The result looks a bit odd:
If I increase the thermal width, this continues to almost a short:
The DRC doesn't complain about this. To prove the DRC is working, I arbitrarily thicken a trace... this is being correctly flagged:
Is this behaviour expected?