Signal integrity, feature request/recommendations

[erik.buerV95QJ]

The following are some recommendations for improving the SI functionality in Fusion.

1) Measure delay, not length.

Meandering is used to match the delay of the traces, not the physical length. The propagation speeds vary over the PCB layers based on the dielectrics in which the fields propagate. E.g. the propagation speed for a microstrip will be greater than for a stripline on an internal layer, due to the difference in effective relative permittivity. By estimating the time delay of a trace, more precise tuning can be accomplished.

The delay is only reported when using the meander tool, it should also be reported when dragging and stretching the traces. Adding colors to the traces based on their compliance with the delay constraints will provide a quick overview of the state of a bus. E.g. red traces for insufficiently short, and green for compliant lengths. (something along those lines)

2) Add support for delay tuning through series components.
Often a series termination, transformer or common-mode-choke is placed in series between the source and destination. Today I would need an extensive excel sheet to tune my signals, most of which have series components.

3) Add support for package delay.

The delay of the chip package also eats into the timing budget. By allowing pin delay to be configured on the package, this skew can be controlled by tuning the traces on the PCB.

4) Add support for layer specific with/spacing constraints on controlled impedance signals.

The required width and spacing for a given impedance vary greatly over the PCB layers based on the laminate material and thickness. Today I have to route signals on a single layer pair in order to use the spacing configuration through the net class. I am not fond of the current net class-based workflow for controlled impedance signals.

5) Specify which method is used, how is the length derived, what is taken into account, what is not.

Do you account for propagation through vias? How is the length measured through bends, arcs etc.? How are pads accounted for? Which models are used for propagation delay calculation? etc.
Whis must be documented in order for users to gain confidence in the tool.

The Eagle post on delay tuning is mixing up impedance and propagation delay. The article needs corrections.

https://www.autodesk.com/products/eagle/blog/length-match-high-speed-nets/

-Erik

[jorge_garcia]

Hi @erik.buerV95QJ ,

Thank you for the excellent suggestions for SI workflows within Fusion 360. This is something that we definitely want to do, however there are other priorities at the moment so I can't offer any ETA on when these things will be implemented even though they are excellent suggestions.

@panpan_fan If you can, make a ticket and link this thread to it. The suggestions here will be useful for whenever the dev team is ready to make signal integrity improvements.

@erik.buerV95QJ In general you are correct in that the goal is to match delay and not length, however under certain constraints matching length will match delay (no layer transitions, same trace architecture for all members of the bus[all stripline, all microstrip, etc.], no width changes along the length of the traces). Even then you would only be able to say that the delays are equal and not what the absolute value of that delay is. IOW, to a first order and under typical conditions matching length will be good enough. I agree it could be much better and someday it will be.

In regards, to the article could you be more specific of the corrections that need to be done. I saw something off in the last paragraph but I think you are pointing out bigger flaws.

Thanks again for these suggestions.

Let me know if there's anything else I can do for you.

Best Regards,