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Placing thermal vias in the SMD contact in a component's footprint

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Message 1 of 6
AdLav
327 Views, 5 Replies

Placing thermal vias in the SMD contact in a component's footprint

Hello,

 

I need to design a component footprint that includes a path for heat dissipation through an SMD contact to the other side of the board. I tried following the guide found here, but that causes the board editor to throw an error saying that there's overlap between the PTH pad and the polygon. I have run through the process, step-by-step, multiple times to ensure I'm doing it correctly and will do so again. If there's a preparatory step that's not listed here or there's just a better way to add thermal vias, I'd appreciate some assistance. I'm quite new to the program, so I'm still getting a handle on everything.

 

Thank you

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Message 2 of 6
butch_berney
in reply to: AdLav

You need to make sure that the Polygon Pour carries the same net name as the PTH pads on the schematic.

I don't think you can have a polygon pour that overlaps an SMD pad in the footprint, but you can overlap the SMD pads in the PCB with a pour, again, as long as the pour has the same net name as the pads.

Good luck!
Message 3 of 6
AdLav
in reply to: butch_berney

Thank you, Butch! It's odd to me that you can't put the PTH's in the footprint polygons (any more, I assume, since they have that tutorial recommending it). It would be convenient to build the thermal vias right into the footprint.
Message 4 of 6
butch_berney
in reply to: AdLav

I’m pretty sure you can put a pour over PTH pads, but not SMD pads. Not sure why…or I could be remembering wrong. Just remember that if you make a pour in the footprint, you will need to manually add the stop layer and if needed, cream layer polygons. In the footprints I’ve done, I turn off the thermal, stop, and cream on the PTH pads. There is also a tip on how to make sure the vias (which are actually pads in the footprint) get covered with solder mask on the bottom side, but I’m not at my computer and don’t remember the details off the top of my head. I’ll post it later.
Message 5 of 6
AdLav
in reply to: AdLav

UPDATE: It appears I had made the foolish assumption that the the Rectangle tool was just a specialised version of the polygon tool and that they would therefore behave the same. As it turns out, rectangles are not polygons and cause the DRC to report an overlap error.

Message 6 of 6
butch_berney
in reply to: butch_berney

To make sure that your vias get covered with solder mask...when you want them to be covered...you need to set the Limit value in the Layer Stack Manager, Masks tab, to be larger than your via size. I usually set mine to 0.4mm since most through hole devices that I use are larger than 0.4mm. Any via smaller than 0.4 will be covered. If you want your PTH pads to be covered, you will need to manually turn off the stop layer in the properties for those pads.

 

Good luck!

butchberney_0-1685468635534.png

 

 

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