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Named Polygons are not updating on Net Merges

Message 1 of 8
315 Views, 7 Replies

Named Polygons are not updating on Net Merges

We have a design block with wide, custom edge fingers that carry power and signals through an flexible PCB LED strip when the blocks are strung together (see pic). Polygons seem like a great way to do the fill and not have rounded ends like traces have.

However, the signal lines are daisy-chained, so each new design block dropped in gets a net name update. we have vias that update just fine on the net merge, but the polygons do not. Not sure if we need to group the vias and polygons (top and bottom) in the design block?

Any insights would help us knock this design out.

Message 2 of 8

Hi @chris_cummingsDT 

Thanks for reporting this.
I try to reproduce your issue but failed. Could you please give more details to show how to reproduce it?
And if you don't mind, could you share your file. It will help a lot.

Haiyuan Lan
Message 3 of 8

Hello, @haiyuan.lanPUMBU ! Thanks for looking into this. I really tried to put together a video I could post to YouTube, but I have never done PC screen capture, and the number of myriad issues related to multi-screen and mic and recording resolution made that not possible for today.

In the attached pic, the design block on the left has native naming. The block on the right has the CLK and D lines renamed after Design Block Insertion. The Polygons did not follow the name changes made in the schematic the way the vias did, but there are total of 4 objects all together; Top and Bottom Polygons and 2 Vias.

You mentioned sharing the file. How would I do that? I am just thinking cloud, libraries, etc where just exporting the .fsch and .fbrd might not get you there.

Message 4 of 8

Hi @chris_cummingsDT 

I think the .fsch and .fbrd will be okay. And could you clarify to rename which CLK and D wire? From the image I can't see the difference.

Haiyuan Lan
Message 5 of 8

Also, I try a little bit and the polygon and via can update well. Could you help to check my steps?
1. the right side is added design block, the left side is local one
屏幕截图 2023-06-13 100517.png
2. In the design block, I rename N$5 to N$55
屏幕截图 2023-06-13 100609.png
3.Switch to brd, you could see the wire and via can update well
屏幕截图 2023-06-13 100653.png polygon agian, the polygon used to be N$5, now both top and bottom polygon can update well
屏幕截图 2023-06-13 100726.png
Not sure do I miss something. Wait for your feedback. Thanks

Haiyuan Lan
Message 6 of 8


I could not directly attach the Eagle Design Block in my reply, so I hope this link is allowed.

Message 7 of 8

Sorry for I can't open the link.
And the best way would be having your original design and a demo video. 
@chris_cummingsDT If you don't mind, could you send your design to my email so that I can have a try. Your design is only for our inner testing.
My email address is sent to you by a private message. Please check.

Haiyuan Lan
Message 8 of 8

OK. So, I think we have an answer and a work-around. The polygons do not update by design. I can't really think of a use-case off the top of my head where a polygon specifically named to match a net name should not update when the net name is changed, but I guess someone had a situation like that.

More importantly, we have 2 possible work-arounds. The initial reason for the polygon was that we could not select flat endcaps for traces, and now that feature works in F360. A second possible solution is to draw a simple line; they now get assigned net names!! Both enhancements in F360 Electronics are very welcome. Thanks to Pawel Sama for all the insights!

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