DRC Trace Clearance Global Change

[RCBakerBorn]

I am wanting to know how to make a global change on the PCB for trace clearance.

We set the minimum clearance in the DRC and clicked apply.

We then ran an error check and the DRC flags all the errors due to the new clearance settings.

How do we auto space between traces, according to the new clearance rules we set, so the errors go away?

[jorge_garcia · Accepted solution]

Hi @RCBakerBorn ,

I hope you're doing well. In this scenario, you have to manually re-route some of the traces. Just having the gap swell could cause traces to go over the edge of the board or run into components. Additionally, how would the new clearance be applied? Do you split the difference and move traces relative to the centerline between them? Do you apply the swell unilaterally? 

I'm just trying to get across that it's not possible to automatically increase the separation between traces in a one-size fits all way.

The safest thing the software can do it let you know where the clearance issues are.

Best Regards,

[RCBakerBorn]

Thank you for your reply Jorge.

[haiyuan.lanPUMBU]

Hi @RCBakerBorn 
I hope I find you well.
As Jorge said, DRC just for checking error, we couldn't make the gap between wire larger.
But there's still one workaround.
When you modify the clearance value, run DRC and violation show up. You could unroute all signal then autoroute, Fusion will follow new clearance value during the autorouting. Or you could just delete some wires which have the violation, then use autoroute again.
Unroute and autoroute cmd are in the Design tab


Hope this help!