any layer stacked micro-via support

[eric_engineer]

I want to do stacked micro-vias with any layer interconnect (sometimes called ELIC).  That's where I can have a stack of micro-vias from any layer to any layer.  So micro vias could go from layer 1-12, 3-5, 4-9, 2-12, etc.  Just any combination of them stacked on top of the other.

Is this possible in this tool?

[matt.berggren]

Thanks for the question.  We are discussing this but given the pretty regular commentary about failures in Class II and  III we aren’t seeing high demand amongst users.  The work is fairly trivial from our end but the demand isn’t high right now so we parked it for a bit while we focus on things with a broader impact.  For example, we are aware that Class III is not yet accepted in virtually any critical systems, nor finding widespread adoption of even Class II for the majority of applications.  I’m confident this will change but even with WSP devices, I’ve yet to see many pin counts high enough to not favor staggered uVias.  I would hope to see better evidence outside of direct wire bonding and the like that led IPC to update the 2226 guidance and EIA or others (perhaps UL) pick this up with mfgs to ensure higher reliability before prioritizing this above other work.  I am also not aware of FAA or MIL would consider this (yet) and would expect that to be a lagging indicator but also a well-researched (one would hope) analysis of the metalization issues at the junctions.  

If I can ask, what is the application and is it something where staggered uVias wouldn’t work?  I am assuming it is but thus far I have seen a bit of high temp MCM (nothing packaged or overmolded rather), some other applications going directly bonded and some memory stacking, but not much else.  I am genuinely curious because it could indicate a trend that leads us to raise the priority and do it right.  I have seen some other implementations but many are pretty weak or downright misleading.  If the aim is to find THE tool that will do it right, then Id suggest we chat and you connect with my team because we are always looking for the real-world use cases to ensure we can build things a wider range of people might then start adopting with confidence.

thanks,

matt - autodesk

[eric_engineer]

Hi Matt,

       ELIC is much more convenient than staggered micro-vias 🙂  It used to be very expensive but the prices have come down dramatically.  We're doing very dense cell-phone style boards where the BGAS have a very high pin count, and are closely spaced. For example our processor has 800 balls on a 12 mil pitch and that's just one part.  The entire board is smaller than a business card so besides losing your mind trying to keep track of the staggering 🙂 There just is not enough space for that kind of approach. I don't think this is niche, but it might not be the kind of thing people use Fusion for.

Best Regards,

-Eric

[jorge_garcia · Accepted solution]

Hi @eric_engineer,

I hope you're doing well. So stacked micro-vias is technically possible in Fusion Electronics, however you will have to use the old school setup string to implement it.  Here's how to access the string field

Now here's how this works in a nutshell. Basically you'll have to define blind vias one layer deep going layer by layer. I'll show you a 6 layer example but the pattern will repeat. For full documentation on how the setup equation see the attached reference. This gives you stacked micro-vias to the center core.

([2:1+[3:2+3*14+15:14]+16:15])

Let me know if there's anything else I can do for you.

Best Regards,

[eric_engineer]

Has this gotten any better? We are crashing into this again this week.

Thank you,

-Eric

[jorge_garcia]

Hello @eric_engineer,

I hope you're doing well. We don't have anything new to report on this front but I'm going to make a detailed report on it to see if we can get a better UX experience for it.

Let me know if there's anything else I can do for you.

Best Regards,