What's new in Fusion Electronics March 2025

[jorge_garcia]

Hello everyone, 

Just wanted to share that latest features that came out with the March release of Fusion.

Import SVG

For some time, many of you have requested the ability to import SVG files into your electronic documents. Now, you have a straightforward method for incorporating a company logo or essential symbols that need to be included in your schematic or PCB. Importing SVG files into your design editor enables precise vector-based graphics for detailed silkscreen work and accurate logo placement, allowing for high scalability. This new feature will also function in the library document symbol and footprint editors.

Designating a Pin as Not Connected in the Schematic

Flagging unconnected pins in a schematic prevents Electrical Rule Check (ERC) errors, ensures accurate netlist generation, and avoids unintended connections during PCB layout, improving overall design clarity. Previously, this capability was only available in the library document symbol editor; with this update, unconnected pins can now be flagged directly within the Schematic. This enhancement not only improves documentation and design workflow but also saves time by eliminating the need to mark unconnected pins as acceptable in the ERC report. Additionally, this action can be performed on a single pin or a selection of pins (via the design manager), ensuring greater accuracy and efficiency in circuit development.

Pick & Place File export update

A Pick and Place (PnP) file is a manufacturing output file that contains precise component placement data for automated PCB assembly machines. It includes details such as component reference designators, X-Y coordinates, rotation angles, and part numbers, ensuring accurate and efficient placement of components onto the PCB. We are happy to inform you that the pick and place output can now include through-hole components (THT). In addition, the components not part of the assembly variant will not be included in the Pick and Place output. These new implementations will assist you in getting accurate manufacturing exports sooner.

Soldermask Default is now Set to “Auto”

A via on a PCB allows electrical signals to pass between different layers, enabling complex multi-layer circuit designs. The solder mask on a PCB insulates and protects copper traces from oxidation, prevents solder bridging, and enhances reliability during assembly. Depending on the design requirements, Vias can be covered by the solder mask (tented) or exposed. We have facilitated a way for you to easily switch without changing the design rule. This feature update provides greater flexibility in your PCB design process, allowing for easy adaptation and reliability requirements.

Image Export command now Considers the Active Layer

Exporting images of your PCB design is essential for documentation, design reviews, and effective communication with manufacturers and assembly teams. In this update, we have enhanced the image export functionality by prioritizing the active layer. This improvement will provide greater accuracy, making it easier for stakeholders to gain precise insights into the design.

Undo Layer Changes

While working with system (1-99) layers, you previously only had the option to restore default settings. In this update, you can undo your latest change without reverting to the default settings, providing you with more options when customizing colors and shades in your layer display panel.

Other Enhancements

• Improved SI Extension – Do not show signal wires over pads and vias​
• Added appropriate error messages when attempting to flip locked components in 3D​
• No more surge of RAM usage when switching tabs frequently​
• After editing the base sketch of 3D PCB holes with reference dimensions, the 2D PCB is now updated correctly​
• Library: Footprints with circles on the Dimension layer work as board outlines now​
• New way to turn all rules on or off from the column header​
• We have begun standardizing the attributes in our component libraries.