VIA in pad

[eric_engineer]

Is it still not possible to place a via in a SMD Pad without a DRC error? In 2024.

[marcocipriani01]

Just set the clearance between vias and SMD pads to 0mm in the Layer Stack Manager, and you're golden.

[eric_engineer]

This is going to ignore spacing problems with regular vias though.  I get that it helps but it's not a solution.

[marcocipriani01]

That's why I always tell JLCPCB to epoxy-fill each and every via on my 6 layers boards. It's free anyway, at least with them, and it saves me from mistakes 😂

[jorge_garcia]

Hello @eric_engineer,

I hope you're doing well. In Electronics, via in pads are best handled as micro-vias. You can set micro-vias in the sizes tab, the key to enabling them is to make sure the min micro via smaller than the minimum drill. 

Always remember that you never have to pre-place vias, the routing engine will let you place them on the center of the pad as long as violations are not incurred. Thinking about it now, you might now have to do the micro-via thing or any other special config. It does work though.

Let me know if you continue to run into problems.

Best Regards,

[eric_engineer]

hi @jorge_garcia I'm still not sure how to do this the right way? It allows me to place the via but complains about SMD overlap. 

[jorge_garcia]

Hi @eric_engineer,

I hope you're doing well. Would you be willing to do a screen capture showing how you got it routed? The DRC rules have been reworked relatively recently I want to make sure this isn't a new DRC issue.

Thank you in advanced @eric_engineer for reaching out.

Let me know if there's anything else I can do for you.

Best Regards,

[eric_engineer]

Sure, whenever you have the time, just let me know. I'm here now, but off tomorrow.

[silvio3105]

Need help with this also. Not sure why F3E gives warning when both via and pad belongs to same net/signal.

[constantin.popescuXD3CL]

Hi @silvio3105,

Are you using any Custom Rules or you have only defined the General Rules? If you are using Custom Rules can you please post some snapshots with the custom copper clearance rules you have defined and I will try to replicate this issue. Otherwise if you can share a simple example that shows this issue that would be very much appreciated. My email address if you decide to send an exmple is: constantin.popescu@autodesk.com

Kind Regards, 

[silvio3105]

DRC rules are "stock". Only vias in pads are the problem for DRC. GND signal in this case.

[constantin.popescuXD3CL]

Hi @silvio3105,

The same signal copper clearance rule works for micro-vias only. You need the vias in pad to be micro-vias for this to work and also the pad-via clearance needs to be set to 0. This is the only way to disable the same signal clearance check. You need to set-up the micro-vias in the Layer Stack Manager if you haven't done it yet in the Via Pairs table.

Please see below snapshots for an example:

The highlighted micro-via from layers Top to Route2 (1-2) is on SMD 5 of component IC2 and there is no violation. Please see the MicroVia definitions in the Layer Stack Manager and also the Minimum Micro Via Drill Diameter value that is set to 20mil and the micro-via diameter is 7.8mil (so smallaer than the minimum). Then in the Design Rules Editor dialog the SMD - Via Clearance  is set to 0mil:

This is currently the only way to get the micro-via in pad to work and no violations to be generated.

I hope this helps. Please let me know if there is anything else I can help you with.

Kind Regards,

[silvio3105]

It helps but SMD-Via clearance will ruin all other (classic) vias? Seems like I'll ignore DRC errors.

[constantin.popescuXD3CL]

Hi @silvio3105,

Actually you can create custom same signal copper clearance rules like this:

1. Use Is Blind Via scope (micro-via scope is not currently allowed in the same signal copper clearance scope and that's a mistake that we will rectify soon) for Object 1 and Is Smd for Object 2 and make the Minimum and Preferred values 0. This will work if we assume that your blind vias span only one dielectric, e.g.: 1-2, 15-16.
2. Use Is Thru Via scope for Object 1 and Is Multi-Layer Object for Object 2 and set the copper clearance to a bigger value, e.g.: 10mil.
3. You can also add another same signal copper clearance rule for Is Smd against Is Pad with a specific clearance value (this will cover the SMD - Pad Clearance).
4. In the General Rules make the: SMD - Pad Clearance Minimum value the smallest so it doesn't interfere with the custom same signal copper clearance rules you have added. 
5. In the General Rules make the: SMD - Via Clearance Minimum value = 0.

I think thes above rules should allow you to control the Via in SMD as well as the clearance between other via types (not micro-vias) and vias or pads, and other via types and smd's.

Some custom copper clearance rule examples below:

SMD - Pad for a specific net-class

Via - Pad in specific signal.

For all the general same signal rules I have made the Minimum vlaue = 0, see below:

I hope this will help you.

Kind Regards,

[panpan_fan]

Hi @silvio3105 

I hope you are doing well!
Today we release Fusion V2.0.20754 and now we support Is Micro Via and Is Copper (Wire, Polygon)  in the scope.

Please have a try, thanks a lot!
Regards,

Panpan Fan

Regards,

Panpan Fan

[silvio3105]

I don't understand what is micro via anymore and what is Is Copper.

- Microvia is diffrent name for via in pad?


Can you provide more info? Thanks.

[jorge_garcia]

Hi @silvio3105 ,

Technically, a micro-via is a special type of blind via which goes 1 layer deep and is often used for via in pad applications

Although that is not only use case.

These very small drills are often made with lasers or very small thin bits.

Let me know if there's anything else I can do for you.

[silvio3105]

- What is "Is Copper" (... "and Is Copper (Wire, Polygon) in the scope.")?
- I still get overlap errors for (normal) via in pad(same net). Is not that fixed in latest update?

[constantin.popescuXD3CL]

Hi @silvio3105,

Via in Pad only works for micro-vias and this hasn't changed. If you create micro-via pairs in the Layer Stack Manager and then use these when you route then there will be no DRC violation. Please see below snapshots:

The 2 vias 1-2 (Top to Route 2) are on signal N$2 the same with the SMD 5. The 2 vias are micro-vias an they are allowed to touch the SMD pad. The other 1-2 micro-via below the SMD 5 is on signal N$9 and you can see that it is not allowed to get any closer to the SMD than the custom copper clearance set in Design Rules, see below:

This is the same signal custom copper clearance that allows micro-via in SMD for signal N$2.

This is different signals custom copper clearance rule that prevents any other smds from touching micro-vias.

I have attached a simple test example that I have used to test this behaviour that you can use as reference.

I hope this helps. Please let me know if there is anythign else I can help you with.

Kind regards,

[constantin.popescuXD3CL]

Hi @silvio3105,

You can also use thru-vias in SMD if you set-up a custom same-signal cospper clearance rules like it is shown below:

You can see that the thru-via that overlaps SMD 8 doesn't have any overlap error. This is in the same example test that I have attached in my previous post.

Kind regards,