Merging Nets on inserted Design Blocks

[chris_cummingsDT]

Attached, please find a PDF of our issue.

We have an RGB Smart LED Controler (LPD8806) and 2 RGB LEDs in a Design Block. We re-use the design block in daisy-chain connectivity style to build out a 500mm strip of 13 DBs. The Data In and Clock In signals feed the IC, and it outputs to the next Design Block via Data Out and Clock Out. 

We number the nets with a 2-digit suffix and the Design Block has -00. Once subsequent blocks are inserted, we spin the numbers on the output side. Our problem is that we need the subsequent block's input to take the net names from the outputs of the previous block. The other direction of net name precedence does not work.

Is there a way to pre-set the precedence in net name survival on a merge?

[chris_cummingsDT]

As an update to this post, We have found another related problem. There seems to possibly be a difference between Control-C / Control-V copy / paste behavior and Right-Click Copy behavior relating to Net Renaming. When we import a Design Block and connect nets in the schematic, only SOME of the segments in the 2D PCB get renamed. Other parts (segments) of the net remain linked to other instances of the Design Block we have inserted.

Sounds crazy, but attached are the Design Block and the Archived Project so you can see it for yourself. If you select the CLKO at the right edge of the 2D PCB, you can see the wide "finger" trace has thinner parts that attach to the via. Those segments are not getting renamed properly.

Please note that the Forum does not support .DB files natively, so I zipped it up with the .f3z of the project.

Thanks, @jorge_garcia and @tasha.addington-ferris