Difficulties on adding spice model

mario.brizida · ‎12-05-2022

Hi,

I'm now trying to make some simulations and realised that my system is not working properly because I'm using standard spice models and not the models of the components I indde use, so I tried ti download manufaturer's spice model of a transistor and was not succeded. Spice model I need is:

**********************************************************
*
* BC846S
*
* Nexperia
*
* General purpose double NPN transistor
* IC   = 100 mA
* VCEO = 65 V 
* hFE  = 110 @ 5V/2mA
* 
*
*
*
* Package pinning does not match Spice model pinning.
* Package: SOT 363
* 
* Package Pin 1;4: Emitter     TR1;TR2  
* Package Pin 2;5: Base        TR1;TR2
* Package Pin 3;6: Collector   TR2;TR1
* 
* 
* Extraction date (week/year): 39/2018
* Spicemodel includes temperature dependency
*
**********************************************************
*#
*
* Diode D1, Transistor Q2 and resistor RQ 
* are dedicated to improve modeling of quasi
* saturation area and reverse mode operation
* and do not reflect physical devices.
*
.SUBCKT BC846S 1 2 3
Q1 1 2 3 Transistor 0.9755
Q2 11 2 3 Transistor 0.0245
RQ 11 1 1693
D1 2 1 Diode
*
.MODEL Transistor NPN
+ IS = 1.089E-014
+ NF = 0.9981
+ ISE = 3.006E-015
+ NE = 1.369
+ BF = 288
+ IKF = 0.08473
+ VAF = 35.12
+ NR = 1
+ ISC = 1.068E-014
+ NC = 1.357
+ BR = 8.655
+ IKR = 0.009746
+ VAR = 25
+ RB = 300
+ IRB = 3.58E-005
+ RBM = 0.8
+ RE = 1.882
+ RC = 0.387
+ XTB = 1.734
+ EG = 1.11
+ XTI = 5.656
+ CJE = 1.284E-011
+ VJE = 0.6863
+ MJE = 0.3393
+ TF = 7.33E-010
+ XTF = 8.656
+ VTF = 2
+ ITF = 0.8548
+ PTF = 0
+ CJC = 3.458E-012
+ VJC = 0.5671
+ MJC = 0.3547
+ XCJC = 1
+ TR = 1.2E-006
+ CJS = 0
+ VJS = 0.75
+ MJS = 0.333
+ FC = 0.9552
*
.MODEL Diode D
+ IS = 1.09E-015
+ N = 0.985
+ BV = 1000
+ IBV = 0.001
+ RS = 2382
+ CJO = 0
+ VJ = 1
+ M = 0.5
+ FC = 0
+ TT = 0
+ EG = 1.11
+ XTI = 3
.ENDS
*
I tried to add spice model for several ways and I always got error.
Could you tell me please, step by step how to do it?

Thank you,
MB

edpataky · ‎01-26-2023

Hello Mario, please save this text as a file called "

BC846S.mdl

Then right click on the part it is associated to, and choose "add spice model" .

You can do this on one part, or select multiple parts to setup for simulation, and do all at once ... right click on the part, or one part in a selection and you should see a table with all the parts and whether they have models mapped or not. Notice it can be convenient also to adjust values of things in the table .. for example the voltage source value would be changed to something like "3V" as opposed to the default value that came from the library.

Make sure you choose the correct simulation type (the system makes a guess based on name and # of pins, but you need to verify) and then click MAP. The MAPping process is to connect the model inputs to your symbol pins, again, the system makes a guess based on name, but it cannot always guess right .. you need to verify .. many times it is right on ..

Depending on the TYPE you select in the table, when you click MAP, you will have several options:

(a) you do not need to provide any file - true for devices with intrinsic models that do not have any parameters like for resistors, capacitors, and inductors.

(b) you need to provide a spice model card, where the format is .model name built-in-type (specs) .. you will have a dialog like below where you can load that file, .. it should be a file named with the same name as in the model. so for example below the file would saved as DMOD.mdl

(c). you need to provide a subcircuit file, where the format is .SUBCKT ... specs ... ending with .ENDs .. again, you will have a dialog where you can load the file ..

NOTE: you can simply paste the text into the dialog as well, just make sure to name it in the dialog "MODEL NAME" exactly the same as in the text of the model "DMOD" in the ex below

The last step is connecting model inputs to pins. In the example below, the model is a diode spice model card and it is being attached to a part with 2 pins with a diode symbol .. so we need to map the model inputs called A and C (anode and cathode) to the part symbol pins, in this case called + and -. Once we do this mapping we are done, and the device is ready for simulation.

Note that ALL devices in the sch need to be mapped, and this is the reason for the table interface .. you can virtually select an entire schematic, and run the add model command (right click on one of the selected parts and choose add model) and you can do your setup for everything in one shot .. We have to do this mapping because of course not all library parts have the same naming for pins, and not all models have the same input ordering, input naming, etc

A couple tips:

the system is smart enough that if you map a spice model to one part in schematic, and you have 10 more instances of them, it will ask if you want to apply to all of them
also note if you do this in schematic, it is ONLY in that schematic .. if you desire, you can do this mapping in library, on the device in exactly the same way, only, it will always include the model if you do it this way, when you place the part (but you can always override in sch if you want)

Please try those steps and let us know if it works for you. Note that clicking the simulation button will run a check whether your SCH is ready for simulation or not, or if models are missing, and it will tell you which parts need to be setup.

Hope this helps!

hupp · ‎09-13-2023

Hello @edpataky ,

Thank you for the explanation above! I am having similar issues trying to map a model to the generic op-amp symbol.

- I first removed the existing SPICE model.
- Next I select "Add Spice Model"
- I then click the Map button and select the .mdl file which I created from a TI TINA file. (Attached below)
- The file is read in but then when I click the Map Pins tab no pins appear in the dialog box.

What am I doing wrong? I appreciate any help you can supply.

Thanks!
Brian

* OPA2863A - Rev. A
* Created by Hasan Babiker; 2022-12-09
* Created with Green-Williams-Lis Current Sense Amp Macro-model Architecture
* Copyright 2022 by Texas Instruments Corporation
******************************************************
* MACRO-MODEL SIMULATED PARAMETERS:
******************************************************
* AC PARAMETERS
**********************
* CLOSED-LOOP OUTPUT IMPEDANCE VS. FREQUENCY (Zout vs. Freq.)
* CLOSED-LOOP GAIN AND PHASE VS. FREQUENCY WITH RL, CL EFFECTS (Acl vs. Freq.)
* COMMON-MODE REJECTION RATIO VS. FREQUENCY (CMRR vs. Freq.)
* POWER SUPPLY REJECTION RATIO VS. FREQUENCY (PSRR vs. Freq.)
* INPUT VOLTAGE NOISE DENSITY VS. FREQUENCY (en vs. Freq.)
**********************
* DC PARAMETERS
**********************
* INPUT COMMON-MODE VOLTAGE RANGE (Vcm)
* GAIN ERROR (Eg)
* INPUT BIAS CURRENT VS. INPUT COMMON-MODE VOLTAGE (Ib vs. Vcm)
* INPUT OFFSET VOLTAGE VS. TEMPERATURE (Vos vs. Temp)
* OUTPUT VOLTAGE SWING vs. OUTPUT CURRENT (Vout vs. Iout)
* SHORT-CIRCUIT OUTPUT CURRENT (Isc)
* QUIESCENT CURRENT (Iq)
**********************
* TRANSIENT PARAMETERS
**********************
* SLEW RATE (SR)
* SETTLING TIME VS. CAPACITIVE LOAD (ts)
* OVERLOAD RECOVERY TIME (tor)
******************************************************
.subckt OPA2863A IN+ IN- VCC VEE OUT
******************************************************
.MODEL R_NOISELESS RES (T_ABS=-273.15)
C_C1 MID CLAMP 1.13E-8
C_C10 MID N42834 1E-15
C_C11 N44757 MID 1E-15
C_C12 MID N45892 1E-15
C_C13 N45974 MID 1E-15
C_C14 MID N56659 1E-15
C_C15 N56721 MID 1E-15
C_C16 MID N61579 1E-15
C_C1A1 N1995214 N1995224 1.592E-8
C_C1A10 N2002402 N2002412 3.003E-11
C_C1A13 N2014228 N2014238 1.592E-13
C_C1A2 N1995184 N1475322 1.061E-11
C_C1A27 N2014170 N2014180 1.447E-6
C_C1A28 MID N2014596 1.592E-13
C_C1A8 N1999301 N706294 1.447E-8
C_C1A9 N2002382 N709248 1.576E-14
C_C33 N406634 0 1E-15
C_C34 N317950 0 1U
C_C35 N406794 0 1E-15
C_C36 N1548814 N1548992 7.958E-13
C_C37 N1549138 N1549254 7.958E-13
C_C38 N1566698 N1566638 4.547E-11
C_C39 N1566868 N1566646 1.592E-13
C_C40 N1573384 N1573324 4.547E-11
C_C41 N1573556 N1573332 1.592E-13
C_C43 MID N1897556 4.45E-13
C_C44 MID N1901998 4.45E-13
C_C45 MID N1902704 4.45E-13
C_C46 MID N886969 4.45E-13
C_C7 N31014 MID 1E-15
C_C8 MID N35813 1E-15
C_C9 MID N38096 1E-15
C_C_CMN MID ESDN 0.877E-12
C_C_CMP ESDP MID 0.877E-12
C_C_DIFF ESDN ESDP 0.3E-12
C_C_VIMON MID VIMON 1E-12
C_C_VOUT_S MID VOUT_S 1E-12
E_E1 N1566698 MID N1566688 MID 1.429E3
E_E10 NOISE_OUT N1549078 N1549254 MID 1
E_E3 N112292 MID OUT MID 1
E_E6 MID 0 N317950 0 1
E_E7 N1566868 MID N1566638 MID 5
E_E8 N1573384 MID N1573374 MID 1.429E3
E_E9 N1573556 MID N1573324 MID 5
G_G10 N2002382 MID N2002412 MID -2.97E2
G_G11 N2002402 MID VCC_B MID -1.687E-3
G_G12 N1897556 MID CLAMP MID -1E-3
G_G15 CLAW_CLAMP MID VSENSE MID -1E-3
G_G16 CL_CLAMP MID CLAW_CLAMP MID -1E-3
G_G2 CMRR_2 N10561 N1475322 MID -1E-3
G_G3 N1995184 MID N1995224 MID -6.667E7
G_G36 VCC_B 0 VCC 0 -1
G_G37 VEE_B 0 VEE 0 -1
G_G6 N25816 N11984 N709248 N706294 -1E-3
G_G78 N1548814 MID N1548704 MID -1.75E-4
G_G8 VCC_CLP MID N35813 MID -1E-3
G_G81 N1549138 MID N1548992 MID -1
G_G82 NOISE_OUT MID N1566646 MID 1E-10
G_G83 ESDN MID N1573332 MID 1E-10
G_G84 VSENSE MID N886969 MID -1E-3
G_G85 N1901998 MID N1897556 MID -1E-3
G_G86 N1902704 MID N1901998 MID -1E-3
G_G87 N886969 MID N1902704 MID -1E-3
G_G88 N1995214 MID ESDP MID -2.626E-8
G_G89 N1999301 MID VEE_B MID -4.257E1
G_G9 VEE_CLP MID N38096 MID -1E-3
G_G90 N2014170 MID CL_CLAMP N896131 -90.91
G_G91 N2014190 MID N2014180 MID -2.815E2
G_G92 N2014228 MID N2014210 MID -1
I_I_B MID NOISE_OUT DC 300E-9
I_I_OS MID ESDN DC 290E-9
I_I_Q VCC VEE DC 750E-6
R_R1 ESDP IN+ R_NOISELESS 10E-3
R_R10 ESDN N11991 R_NOISELESS 1E-3
R_R107 VCC_B 0 R_NOISELESS 1
R_R108 N317950 0 R_NOISELESS 1E12
R_R109 VEE_B 0 R_NOISELESS 1
R_R11 N2002402 MID R_NOISELESS 1
R_R110 VCC_B N406634 R_NOISELESS 1E-3
R_R111 N406634 N317950 R_NOISELESS 1E6
R_R112 N317950 N406794 R_NOISELESS 1E6
R_R113 N406794 VEE_B R_NOISELESS 1E-3
R_R161 MID ESDP R_NOISELESS 650.9E6
R_R169 ESDN MID R_NOISELESS 650.9E6
R_R170 ESDP ESDN R_NOISELESS 206.9E3
R_R182 MID N1548704 1E12 TC=0,0
R_R183 MID N1566688 1E12 TC=0,0
R_R184 MID N1573374 1E12 TC=0,0
R_R190 MID VSENSE R_NOISELESS 1E3
R_R191 MID N1897556 R_NOISELESS 1E3
R_R192 MID N1901998 R_NOISELESS 1E3
R_R193 MID N1902704 R_NOISELESS 1E3
R_R194 MID N886969 R_NOISELESS 1E3
R_R198 N1995214 MID R_NOISELESS 1
R_R199 N1999301 MID R_NOISELESS 1
R_R1A N2014180 N2014170 R_NOISELESS 10K
R_R1A1 N1995214 N1995224 R_NOISELESS 1E8
R_R1A10 N2002402 N2002412 R_NOISELESS 1E8
R_R1A14 N1999301 N706294 R_NOISELESS 1E8
R_R1A15 N2014238 N2014228 R_NOISELESS 10K
R_R1A2 N1995184 N1475322 R_NOISELESS 1E8
R_R1A9 N2002382 N709248 R_NOISELESS 1E8
R_R2 ESDN IN- R_NOISELESS 10E-3
R_R200 N2002382 MID R_NOISELESS 1
R_R201 N2014210 N2014190 R_NOISELESS 2.4E5
R_R202 MID N2014190 R_NOISELESS 1
R_R203 MID N2014170 R_NOISELESS 1
R_R204 MID N2014228 R_NOISELESS 1
R_R21 N11984 N25816 R_NOISELESS 1E3
R_R25 MID N28602 R_NOISELESS 1E9
R_R26 N30136 MID R_NOISELESS 1E9
R_R27 MID N30913 R_NOISELESS 1
R_R28 N31014 N30913 R_NOISELESS 1E-3
R_R29 N35669 VCC_B R_NOISELESS 1E3
R_R2A1 N1995224 MID R_NOISELESS 1.001E5
R_R2A10 N2002412 MID R_NOISELESS 1.767E2
R_R2A13 MID N2014238 R_NOISELESS 2E4
R_R2A2 N1475322 MID R_NOISELESS 1.5
R_R2A23 MID N2014180 R_NOISELESS 3.504E1
R_R2A8 N706294 MID R_NOISELESS 1.1E-2
R_R2A9 N709248 MID R_NOISELESS 3.378E5
R_R3 N1995184 MID R_NOISELESS 1
R_R30 N35813 N35669 R_NOISELESS 1E-3
R_R31 VCC_CLP MID R_NOISELESS 1E3
R_R32 N38050 VEE_B R_NOISELESS 1E3
R_R33 N38096 N38050 R_NOISELESS 1E-3
R_R34 VEE_CLP MID R_NOISELESS 1E3
R_R35 MID VCC_CLP R_NOISELESS 1E9
R_R36 N42663 MID R_NOISELESS 1
R_R37 N42834 N42663 R_NOISELESS 1E-3
R_R38 N44757 N44799 R_NOISELESS 1E-3
R_R39 MID N44799 R_NOISELESS 1
R_R40 MID VEE_CLP R_NOISELESS 1E9
R_R41 MID N50645 R_NOISELESS 1E9
R_R42 N45856 MID R_NOISELESS 1
R_R43 N45892 N45856 R_NOISELESS 1E-3
R_R44 N45974 N45986 R_NOISELESS 1E-3
R_R45 MID N45986 R_NOISELESS 1
R_R46 MID N48550 R_NOISELESS 1E9
R_R49 MID N56919 R_NOISELESS 1E9
R_R5 MID N2014512 R_NOISELESS 1
R_R50 N56635 MID R_NOISELESS 1
R_R51 N56659 N56635 R_NOISELESS 1E-3
R_R52 N56721 N56733 R_NOISELESS 1E-3
R_R53 MID N56733 R_NOISELESS 1
R_R54 MID N56891 R_NOISELESS 1E9
R_R55 N61579 VSENSE R_NOISELESS 1E-3
R_R60 MID AOLNET R_NOISELESS 1E6
R_R61 MID CLAMP R_NOISELESS 1E6
R_R65 MID CLAW_CLAMP R_NOISELESS 1E3
R_R66 MID CL_CLAMP R_NOISELESS 1E3
R_R7 N2014596 N2014210 R_NOISELESS 10E3
R_R8 N10561 CMRR_2 R_NOISELESS 1E3
R_R81 MID N110431 R_NOISELESS 1E9
R_R83 MID N112292 R_NOISELESS 1E9
R_R9 CMRR_2 N11984 R_NOISELESS 1E-3
R_RDUMMY1 MID N896131 R_NOISELESS 2E4
R_RL1 N1548814 MID R_NOISELESS 1
R_RL10 N1566698 N1566638 R_NOISELESS 10E3
R_RL11 MID N1566638 R_NOISELESS 7.005
R_RL12 N1566868 N1566646 R_NOISELESS 10E3
R_RL13 MID N1566646 R_NOISELESS 2.5E3
R_RL14 N1573384 N1573324 R_NOISELESS 10E3
R_RL15 MID N1573324 R_NOISELESS 7.005
R_RL16 N1573556 N1573332 R_NOISELESS 10E3
R_RL17 MID N1573332 R_NOISELESS 2.5E3
R_RL3 N1548814 N1548992 R_NOISELESS 10E3
R_RL4 MID N1548992 R_NOISELESS 7.407E3
R_RL6 N1549138 MID R_NOISELESS 1
R_RL7 N1549138 N1549254 R_NOISELESS 10E3
R_RL8 MID N1549254 R_NOISELESS 7.407E3
R_RX1 N896131 N2014512 R_NOISELESS 2E5
R_R_VIMON VIMON N110431 R_NOISELESS 300
R_R_VOUT_S VOUT_S N112292 R_NOISELESS 300
V_VCM_MAX N30136 VCC_B 0.2
V_VCM_MIN N28602 VEE_B -0.2
V_V_GRN N56891 MID -110
V_V_GRP N56919 MID 110
V_V_ISCN N48550 MID -45
V_V_ISCP N50645 MID 45
X_AOL_1 N31014 N11991 MID AOLNET AOL_1
X_CLAWN MID VIMON VEE_B N38050 CLAWN_OPA2863A
X_CLAWP VIMON MID N35669 VCC_B CLAWP_OPA2863A
X_CLAW_AMP VCC_CLP VEE_CLP VOUT_S MID N42663 N44799 CLAMP_AMP_LO_OPA2863A
X_CLAW_SRC N42834 N44757 CLAW_CLAMP MID CLAW_SRC_OPA2863A
X_CL_AMP N50645 N48550 VIMON MID N45856 N45986 CLAMP_AMP_LO_OPA2863A
X_CL_SRC N45892 N45974 CL_CLAMP MID CL_SRC_OPA2863A
X_ESD_IN ESDN ESDP VCC VEE ESD_IN_OPA2863A PARAMS:
X_ESD_OUT OUT VCC VEE ESD_OUT_OPA2863A PARAMS:
X_GR_AMP N56919 N56891 N61579 MID N56635 N56733 CLAMP_AMP_HI_OPA2863A
X_GR_SRC N56659 N56721 CLAMP MID GR_SRC_OPA2863A
X_H3 OUT N896131 N110431 MID 08_OP_AMP_COMPLETE_H3_OPA2863A
X_IQ_N MID VIMON MID VEE IQ_SRC_OPA2863A
X_IQ_P VIMON MID VCC MID IQ_SRC_OPA2863A
X_I_NN ESDN MID FEMT_OPA2863A PARAMS:
X_I_NN1 ESDN MID FEMT2_OPA2863A PARAMS:
X_I_NP NOISE_OUT MID FEMT_OPA2863A PARAMS:
X_S2 ESDN ESDP ESDN ESDP 08_OP_AMP_COMPLETE_S2_OPA2863A
X_S3 ESDP ESDN ESDP ESDN 08_OP_AMP_COMPLETE_S3_OPA2863A
X_U1 ESDP N1549078 VNSE_OPA2863A PARAMS:
X_U2 AOLNET MID CLAMP MID AOL_2_OPA2863A
X_U3 MID NOISE_OUT VCC VEE IB_VS_VCM_OPA2863A
X_U4 MID ESDN VCC VEE IB_VS_VCM_OPA2863A
X_VCM_CLAMP N25816 MID N30913 MID N30136 N28602 VCM_CLAMP_OPA2863A
X_VOS_DRIFT N10561 NOISE_OUT VOS_DRIFT_OPA2863A
X_ZO_SRC N2014238 MID MID N2014512 ZO_SRC_OPA2863A
.ENDS OPA2863A
*
.SUBCKT 08_OP_AMP_COMPLETE_H3_OPA2863A 1 2 3 4
H_H3 3 4 VH_H3 -1E3
VH_H3 1 2 0V
.ENDS 08_OP_AMP_COMPLETE_H3_OPA2863A
*
.SUBCKT 08_OP_AMP_COMPLETE_S2_OPA2863A 1 2 3 4
S_S2 3 4 1 2 _S2
RS_S2 1 2 1G
.MODEL _S2 VSWITCH ROFF=1E12 RON=50 VOFF=0.9 VON=1
.ENDS 08_OP_AMP_COMPLETE_S2_OPA2863A
*
.SUBCKT 08_OP_AMP_COMPLETE_S3_OPA2863A 1 2 3 4
S_S3 3 4 1 2 _S3
RS_S3 1 2 1G
.MODEL _S3 VSWITCH ROFF=1E12 RON=50 VOFF=0.9 VON=1
.ENDS 08_OP_AMP_COMPLETE_S3_OPA2863A
*
.SUBCKT AOL_1 VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1E-4
.PARAM IPOS = .5
.PARAM INEG = -.5
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS AOL_1
*
.SUBCKT AOL_2_OPA2863A VC+ VC- IOUT+ IOUT-
.PARAM GAIN = -37.01776E-3
.PARAM IPOS = 1.2
.PARAM INEG = -1.2
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS AOL_2_OPA2863A
*
.SUBCKT CLAMP_AMP_HI_OPA2863A VC+ VC- VIN COM VO+ VO-
.PARAM G=10
GVO+ COM VO+ VALUE = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}
GVO- COM VO- VALUE = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}
.ENDS CLAMP_AMP_HI_OPA2863A
*
.SUBCKT CLAMP_AMP_LO_OPA2863A VC+ VC- VIN COM VO+ VO-
.PARAM G=1
GVO+ COM VO+ VALUE = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)}
GVO- COM VO- VALUE = {IF(V(VIN,COM)<V(VC-,COM),((V(VC-,COM)-V(VIN,COM))*G),0)}
.ENDS CLAMP_AMP_LO_OPA2863A
*
.SUBCKT CLAWN_OPA2863A VC+ VC- IOUT+ IOUT-
G1 IOUT+ IOUT- TABLE {(V(VC+,VC-))} =
+(0, 1.139E-4)
+(30, 4.466E-4)
+(38, 5.623E-4)
+(40, 6.057E-4)
.ENDS CLAWN_OPA2863A
*
.SUBCKT CLAWP_OPA2863A VC+ VC- IOUT+ IOUT-
G1 IOUT+ IOUT- TABLE {(V(VC+,VC-))} =
+(0, 1.3E-4)
+(4, 1.598E-4)
+(20, 3.185E-4)
+(30, 4.705E-4)
+(38, 6.66E-4)
+(40, 7.696E-3)
.ENDS CLAWP_OPA2863A
*
.SUBCKT CLAW_SRC_OPA2863A VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1
.PARAM IPOS = 230E-3
.PARAM INEG = -230E-3
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS CLAW_SRC_OPA2863A
*
.SUBCKT CL_SRC_OPA2863A VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1
.PARAM IPOS = 460E-3
.PARAM INEG = -460E-3
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS CL_SRC_OPA2863A
*
.SUBCKT ESD_IN_OPA2863A ESDN ESDP VCC VEE
.MODEL ESD_SW VSWITCH(RON=50 ROFF=1E12 VON=500E-3 VOFF=450E-3)
S1 VCC ESDN ESDN VCC ESD_SW
S2 VCC ESDP ESDP VCC ESD_SW
S3 ESDN VEE VEE ESDN ESD_SW
S4 ESDP VEE VEE ESDP ESD_SW
.ENDS ESD_IN_OPA2863A
*
.SUBCKT ESD_OUT_OPA2863A OUT VCC VEE
.MODEL ESD_SW VSWITCH(RON=50 ROFF=1E12 VON=500E-3 VOFF=450E-3)
S1 VCC OUT OUT VCC ESD_SW
S2 OUT VEE VEE OUT ESD_SW
.ENDS ESD_OUT_OPA2863A
*
.SUBCKT FEMT_OPA2863A 1 2
.PARAM FLWF=0.1
.PARAM NLFF=24.67E3
.PARAM NVRF=286.6
.PARAM GLFF={PWR(FLWF,0.25)*NLFF/1164}
.PARAM RNVF={1.184*PWR(NVRF,2)}
.MODEL DVNF D KF={PWR(FLWF,0.5)/1E11} IS=1.0E-16
I1 0 7 10E-3
I2 0 8 10E-3
D1 7 0 DVNF
D2 8 0 DVNF
E1 3 6 7 8 {GLFF}
R1 3 0 1E9
R2 3 0 1E9
R3 3 6 1E9
E2 6 4 5 0 10
R4 5 0 {RNVF}
R5 5 0 {RNVF}
R6 3 4 1E9
R7 4 0 1E9
G1 1 2 3 4 1E-6
.ENDS FEMT_OPA2863A
*
.SUBCKT FEMT2_OPA2863A 1 2
.PARAM FLWF=0.1
.PARAM NLFF=3.47E4
.PARAM NVRF=314
.PARAM GLFF={PWR(FLWF,0.25)*NLFF/1164}
.PARAM RNVF={1.184*PWR(NVRF,2)}
.MODEL DVNF D KF={PWR(FLWF,0.5)/1E11} IS=1.0E-16
I1 0 7 10E-3
I2 0 8 10E-3
D1 7 0 DVNF
D2 8 0 DVNF
E1 3 6 7 8 {GLFF}
R1 3 0 1E9
R2 3 0 1E9
R3 3 6 1E9
E2 6 4 5 0 10
R4 5 0 {RNVF}
R5 5 0 {RNVF}
R6 3 4 1E9
R7 4 0 1E9
G1 1 2 3 4 1E-6
.ENDS FEMT2_OPA2863A
*
.SUBCKT GR_SRC_OPA2863A VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1
.PARAM IPOS = 3
.PARAM INEG = -3
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS GR_SRC_OPA2863A
*
.SUBCKT IB_VS_VCM_OPA2863A V+ V- REF+ REF-
G1 V+ V- TABLE {(V(REF+, V-))} =
+(-0.2, -525E-9)
+(0.95, -525E-9)
+(1.5, 0)
I1 V+ V- 0
.ENDS IB_VS_VCM_OPA2863A
*
.SUBCKT IQ_SRC_OPA2863A VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1E-3
G1 IOUT+ IOUT- VALUE={IF( (V(VC+,VC-)<=0),0,GAIN*V(VC+,VC-) )}
.ENDS IQ_SRC_OPA2863A
*
.SUBCKT VCM_CLAMP_OPA2863A VIN+ VIN- IOUT- IOUT+ VP+ VP-
.PARAM GAIN = 1
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VIN+,VIN-),V(VP-,VIN-), V(VP+,VIN-))}
.ENDS VCM_CLAMP_OPA2863A
*
.SUBCKT VNSE_OPA2863A 1 2
.PARAM FLW=1
.PARAM NLF=42.18
.PARAM NVR=4.3
.PARAM GLF={PWR(FLW,0.25)*NLF/1164}
.PARAM RNV={1.184*PWR(NVR,2)}
.MODEL DVN D KF={PWR(FLW,0.5)/1E11} IS=1.0E-16
I1 0 7 10E-3
I2 0 8 10E-3
D1 7 0 DVN
D2 8 0 DVN
E1 3 6 7 8 {GLF}
R1 3 0 1E9
R2 3 0 1E9
R3 3 6 1E9
E2 6 4 5 0 10
R4 5 0 {RNV}
R5 5 0 {RNV}
R6 3 4 1E9
R7 4 0 1E9
E3 1 2 3 4 1
.ENDS VNSE_OPA2863A
*
.SUBCKT VOS_DRIFT_OPA2863A VOS+ VOS-
.PARAM DC = 10E-6
.PARAM POL = 1
.PARAM DRIFT = 0.4E-6
E1 VOS+ VOS- VALUE={DC+POL*DRIFT*(TEMP-27)}
.ENDS VOS_DRIFT_OPA2863A
*
.SUBCKT ZO_SRC_OPA2863A VC+ VC- IOUT+ IOUT-
.PARAM GAIN = 1.5
.PARAM IPOS = 20E3
.PARAM INEG = -20E3
G1 IOUT+ IOUT- VALUE={LIMIT(GAIN*V(VC+,VC-),INEG,IPOS)}
.ENDS ZO_SRC_OPA2863A
*

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Difficulties on adding spice model

Difficulties on adding spice model

Difficulties on adding spice model