USB Type C super-speed routing doubts

[Anonymous]

Hi All

I have designed a USB - USB type C receptacle pass-through board. I have started routing the 90R controlled impedance tracks for the USB. I've got the information from the manufacturer to use a trace width of 0.22mm and trace spacing of 0.125mm to achieve 90R impedance. I heard D1_P and D1_N needs to be short to enable the flipping feature. It is a four layer board. I am attaching the schematic and board layout.  Could anyone guide/help me with the layout? Is that correct?

Thanks

[Anonymous]

1. You can use all sorts of track dimensions and spacing to achieve the impedances required.
You need to use an EDGE COUPLED MICROSTRIP IMPEDANCE CALCULATOR to do so in this situation.
https://www.eeweb.com/tools/edge-coupled-microstrip-impedance
https://www.everythingrf.com/rf-calculators/differential-microstrip-impedance-calculator

Using the specified measurements from the manufacturer will rely on you getting everything else correct as per their evaluation and test results.  It is always wise to recalculate these to double and triple check.  Given that your board layout does not seem too critical as it is fairly short and straightforward.  Ultimately the criticality of your PCB will depend on the lengths and qualities of the cables on either side that make up the entire USB path.   if these are unknown you should aim to optimise as best as possible.
2. The most important aspects are dependant on the PCB lay-up (characteristics and thickness of all PCB materials).  And this is critical to determining the correct impedance layout, that suits your application and PCB layout.

3. The thickness of the outside to nearest inner layer is the most important dimension and the distance between the two inner layers (and as a result of the entire board thickness) is the least important.  Of course, this means that the USB traces should be only run on the outside layers.  Which it appears you have done. No info on inner layers of the 4 layer board provided.
4. Generally, you should never run USB diff pairs on inner layers as the remaining via lengths from inner to outer layers create RF stubs that create standing wave reflections.
5. The other crucial thing is to avoid breaks in the ground plane which is provided by the inner layers.  And if they are necessary they need to be supported by some suitable high-frequency coupling which can be difficult especially on inner layers.

A lot more info is needed to make further assessments.

[Anonymous]

Thanks for your reply.

1. I have used the above-mentioned calculator. I am getting the correct 90R impedance. Impedance calculator

I've taken unbroken ground plane underneath layer 1 and above layer 4 (basically, layer 2 is ground referenced to layer 1 and layer 3 is ground referenced to layer 4)

Did you have a look at D1_P and D1_N? are they routed correctly for enabling plugin features? I heard the USB C works reverse and So I need to short that lines.

Please let me know if you need further info to make the USB-C work.

Thanks for your help!!! 

[Anonymous]

Some comments/feedback...

1. Make sure the PCB stack-up your working with (in design) is actually affordable easily obtainable from a PCB manufacturer of choice.  i.e.
http://support.seeedstudio.com/knowledgebase/articles/1096429-what-is-the-stack-up-of-4-6-8-layers-b...
https://www.pcbway.com/multi-layer-laminated-structure.html
If you can use a standard/default stack-up then it will cost a lot less to manufacture especially in small qty.

You can probably forgo impedance control also if you only have short tracks such as this.

2. If you can afford to make inter-track spacing a minimum of 6mil you will also reduce cost significantly.  Or at least go to 5mil and then you will have a slight excess in cost over 6mil. 

Going under 5mil is usually very expensive.   Read the note at the bottom of the second calculator (the one you used and repeated here)

Differential Microstrip Impedance

An edge coupled differential microstrip transmission line is constructed with two traces on the same reference plane. These lines are placed on a dielectric material of height h and there is also some coupling between the lines. It is good practice to match differential trace length and to keep the distances between the traces consistent.

As can be seen from the formula below when d decreases, while keeping h constant, differential impedance decrease. The differential impedance depends upon the D/H ratio. For this calculation, the units of d,h, t and w can be ignored as long as they have the same units (mils, mm, inches).
3. Now check the Note at the top of that calculator.  It says it works for W/H < 1  (i.e. W < H).  Which means that the trace width (W) has to be less than outer to inner layer thickness (H) for the results to be valid (a bad calculator which I will not use again).  And your specs/calculations do not match this criterion i.e. 8.66mil(W) > 7.08mil(H)
If you plug your supplied numbers into the other calculator you get a different impedance.

Refer to the attached images.  First one is the different result due to this limitation on the second calculator. Also, the second attached image dimensions at PCB way for their default 1.6mm stack-up that seems to work out pretty close.

 
4. Note also: The via hole size you have of 0.2mm(7.87mil) is also very small and needs to be around 0.3mm(11.8mil) to be more cost-effective in production.  Note that at these sizes the size does not affect the impedance significantly here.

5. The stack-up you appear to have specified of 1oz copper on all layers all the way through can be unusual.  Often, inner-layers are thinner than outer (see links above).  But PCB-Way has an option for 1oz inners.  But bear in mind this also is not relevant to these particular impedance calculations, just making sure you have planned for production properly.

6. Referring to the standard http://www.usb.org/developers/usbtypec/  (link).  If the two connectors are both Type-C as they appear in schematic then they should just match pin for pin.  I am not aware of any differences needed.  It gets a lot more tricky when you go from USB-C to another type of USB connector as you have to add in Pull up or Pul Down resistors to indicate to the Type-C connector what is occurring as in Host (PU) and Device (PD) on CC (orientation) pins. If your concern over these other USB lines has a reference please provide it.

[Anonymous]

I had another look at the schematic and PCB and I now see that the D1_N & D1_P should NOT be run as you have done.  That is, you have joined them and crossed-them over.  This will cause significant problems.   As far as I can see you should just run separate diff pairs for each of these from the same pins on each connector to the other as your device seems to be an intermediary connector rather than an end-point device or a source host.  I.e. Do not cross them over at all or join together. Basically, it should just be like wiring in an extension of the existing wires in a cable.  That is, any USB-C trickery will be done on the source and end-point.

Also on the impedance, the spec says the impedance needs to fall within the 75R to 105R range which is like 90R+/-15R (or approx 15% error margin).  So under most PCB manufacturing circumstances, this will not mean you need to be too critical about the initial 90R spec. That is an initial design of +/- 5% should be OK ie 86R to 94R will work and still allow for  +/- 10% error.  So you should NOT need impedance control options during manufacturing.

[Anonymous]

It is really a great explanation with detail. Many thanks. 

1.  Yes, I can understand but this is the thickness I've got from the manufacturer. But I am not sure it is cheap or not. I need to ask them. It is a good point to consider. 

2. (a)Are you talking about the Trace separation (d)?  (inter-track spacing?). I've taken trace separation of about 4.92mils(0.125mm) as per the manufacturer's advice which is slightly fewer than 5mils(0.127mm). Do you think this needs to be significantly considered? I can ask the manufacturer.

    (b)Yes, I agree with you. Sorry I didn't notice as well. Thanks for letting me know. My calculations don't match for the second calculator. Yes, I've double checked the differential trace length and distances between the traces consistent using the meander tool in eagle. It seems to be 100% or 99.8%. is that ok?

3. You are right I've tried this https://www.eeweb.com/tools/edge-coupled-microstrip-impedance before and got the wrong results but thought every manufacturer uses a different tool to calculate the impedance. I got your point with the default PCB way stack-up. I've already laid out the PCB using the measurements I have shown you. I am wondering why my manufacturer gave those measurements?

4. That is my bad I've used 0.3mm via sorry but posted you wrong image.

5. Actually, this is the first time I am laying four-layer PCB. So to make sure I've got information from ZOT engineering capabilities. My previous colleague has laid out these connections before but it failed to work at super speed it is working at high speed and the USB cable is not working reverse. That is the reason why I have picked all 1oz layers and fixing it.

6. I heard that the processor has a PU (host) and the Device has a PD. So I thought that no need for PU and PD. Moreover, it is a wire connection. It was working fine with the high speed before. Do you think still needs to be considered?

Great thanks!!!

[Anonymous]

Regarding D1_P, D1_N and D2_P, D2_N 

This is the previous connection used for both schematic and board layout but it is failed to work reverse. It was working only one side. I got advise from another forum to enable plugin features on both sides I should sort them together that is the reason I have done that. See below image of the previous version. Please let me know if this is correct or not. Also why the reverse function wasn't working in that vesrion?

Separately created D1 and D2 pairs for positive and negative.

Yellow lines for D1_P & D1_N, Green lines for D2_P & D2_N.

It is really a great help at this time to start with 4 layer PCB.

Again thanks for your help!!!

[havlicek6TH3H]

Hi,

I use Saturn PCB design tool for impedance calculation etc. https://www.saturnpcb.com/pcb_toolkit.htm

Best Vojta

[Anonymous]

That original ("previous" i.e. failed) design you posted looks just like the way I would have run the USB2 lines i.e. D1_P & D1_N, with separate D2_P & D2_N also. As I was trying to describe in the previous reply. 

---

@Anonymous wrote:

Regarding D1_P, D1_N and D2_P, D2_N 

This is the previous connection used for both schematic and board layout but it is failed to work reverse. It was working only one side.

The reason it may not have worked in reverse is also possibly something to do with an issue on the host or device end or the interconnecting cables.  I hope you have actually tried the same test without the device in the circuit and make sure it does work as expected in that scenario to help isolate where the problem is/was.  Be sure to test separately (with the device left out) with both cables you use in the in-circuit test.

That test/problem aside, if the original board was laid out like this (latest) post and did not work in reverse it will probably be a problem with impedance/manufacture (less likely) or some kind of fault (short/open circuit- much more likely) in the reverse connection in the actual test board.  Remember in reverse it will use the alternative USB2 paths, so working one way and not the other is not likely to be the tracks but some problem with the design or possibly production of this USB-C interconnect device.  Ie. a track touching a metal case due to track layout (short), a manufacturing error (poor bonding/solder bridge/lack of solder etc), or a larger than expected solder mask opening. Be very careful to follow the design requirements in the datasheets including track layout restrictions from the connector manufacturer/supplier to make sure unexpected results do not occur.  Sometimes solder masks are not perfect either at providing insulation.  You may be able to re-test and old board using some Kapton (high temp tape) to add additional insulation from connector cases, where you might suspect a problem (with associated remounting/soldering).

Your latest design might work but it will introduce a lot of reflections and impedance mismatching and IMHO is really just a bad idea trying to patch some other issue.

Besides, it appears from another of your comments that Superspeed failed altogether, which has NOTHING to do with the USB2 lines (i.e. they are not used in Superspeed mode).

@Anonymous wrote:

failed to work at super speed it is working at high speed

Perhaps again due to cabling issues (prove they work well without the device in-circuit).  The problem for valid testing is you will have only 1 cable without the device in-circuit and 2 cables with.   So be sure to make sure you get two short (say 50cm) cables to do the in-circuit test then test with one only.  If that works then test with another double length one (i.e. 2 x 50cm = 1M) from the same cable

manufacturer with same specs.   If that works then add the device it between the two 50cm cables and test again.

BTW I was talking about open space (copper removed) between two adjacent tracks.

On the impedance calculators, and after noticing these discrepancies, I have now surveyed about 20 different ones myself today (including the Saturn PCB application) and they seem to clump into two distinctly different groups that have a significant difference, that I can't yet explain.  Possibly due to two different formula sources. But for some reason, they are about 20% different in the scenario I have been using for USB3.  Now I am a little concerned and if I find an answer/reason I will post it here.

This may be helpful for you or others looking at this thread: https://www.youtube.com/watch?v=BlHLmQ2HO1w

Hint: The guy speaks really slow so play at 1.5x in Youtube settings.

[Anonymous]

Also are you willing to share those Type-C connector footprints as they might be useful, along with details of the source for the connectors?  Many thanks, Rod.

[Anonymous]

I will share the footprint as soon as possible.

Great thanks

[Anonymous]

I just edited my latest post again to fix a few issues, so be sure you read it again.
Thanks on the footprints.

[Anonymous]

Ok I will do.

[Anonymous]

Refer to that video on the question for 2. "100% or 99.8%. is that ok?"  The answer is absolute difference matter rather than relative % values. It is a matter of clock timings and electron traversal speeds as in the less than 1 nanosecond and into the picosecond area usually.  So the specs are usually around 25 mil difference in track lengths cumulative (ie at a maximum), regardless of if the track lengths are 4 inches long (100mm) or 0.5 inches (12mm).  As a comparison a via length (top to bottom) on a 1.6mm board thickness is around 63mil so about half a board thickness difference.  Which is why all differential pairs should have exactly the same number of vias.  This again may be an issue you are facing at SuperSpeed but looks unlikely on this board. 
What does look like it might be a problem, which is another hidden problem, may be that you need ground plane through holes adjacent to the transition from top to bottom layers as you need to JOIN the two inner ground plane layers at or as near as possible to those transition points and this may be your problem for SuperSpeed.

While it looks like the previous designer knew this, he has not done it perfectly and it appears your changes are not done well.  See the attached image for some possible issue that could be done better.
I hope that helps

[Anonymous]

Great thanks.

Please see the below footprint for vertical and horizontal USB connectors

Vertical USB

Horizontal USB

Advised Layout

From your advised layout I can move Tx1_P and Tx1_N. But I am very concerned about the whole D1_N line. Could you please roughly sketch/guide me where to move that line and Via?

[Anonymous]

Great thanks.

Please see the below footprint for vertical and horizontal USB connectors

Vertical USB

Horizontal USB

Advised Layout

From your advised layout I can move Tx1_P and Tx1_N. But I am very concerned about the whole D1_N line. Could you please roughly sketch/guide me where to move that line and Via?

[Anonymous]

Hi Dhinesh:

By sharing the 2 x footprint, I meant as a library [.lbr] file and not as an image.
If you are not sure about publicly doing so you can always personal message me.

If you share the whole board [.brd] (+.sch if you like) file I can fix the problems with vias and track routes.
That will be much easier than documenting otherwise.

I can also get the footprints (connector packages) direct from the .brd file.

Rod

[Anonymous]

I got your files and I can now/have checked the datasheets that correspond to the two connectors.  Here is a core problem I suspect.  The datasheet shows a large no track layout (restricted to GND only) area for PCB tracks under the metal shell of the horizontal connector. Refer to the full document here: https://www.molex.com/pdm_docs/sd/1054500101_sd.pdf

I made a lot of changes to accommodate this restricted area and also to correct for equal numbers of vias and remove as many reflective paths on D1 (usb2) as possible.  I would still prefer the older D1 + D2 (i.e two alternate USB2 paths s per original) layout but have made the changes to accommodate what you wanted.  It will likely work but I stress it is NOT Ideal and not what I would have done. A closer look.  I will email the files. Rod.

Closeup

 Note the two areas where the USB2 cross-overs are done. This is the correct way to use equal numbers of vias.  One is tighter in space than other and not ideal.

Tight with less than ideal but OK layout!A much more ideal crossover

[Anonymous]

Potential shorts due to connector restriction on PCBThese restricted area mistakes will almost definitely explain the problem at SuperSpeed because even if the Solder Masks provided perfect insulation for a DC test, the solder-mask when sandwiched closely between a GND'ed connector shell  and an underlying pad and with the 5Ghz+ differential transmission lines line of USB3, it acts like a capacitor dielectric and transmits the signal to a ground plane. I.e massively changes the intended Zo  (impedance of the lines) effectively shorting them to GND at the RF (Radio Freq) speeds of USB3.

[Anonymous]

Rod

Perfect!!! this would fix the issue. 

I am getting some errors while opening the .sch and .brd file which you've sent me.

Board layout error

Schematic error

Is that layer selection issue?