"No pins on net x" after deleting net from a design block

[Anonymous]

I had an existing design in a project I wanted to use in a different project so I successfully created a design block. For ease of conversation let's say the design block consisted of a chip U1, with a dozen named nets (VCC, GND, NetName1, NetName2, NetName3,...) and a handful of other parts (Resistors, Capacitors, etc).

In the new project schematic I placed the design block and finished the new design. Run ERC and get "Only one pin on net NetName1" because in the new project I didn't need ALL of the nets. So I used the delete tool to remove NetName1 from U1.

Now, when I run ERC I get warning "No pins on net NetName1". The only instance of this net was deleted so it is complaining about a net that does not actually exist or is now invisible? I think perhaps this is an error with design blocks?

The ERC warning does not list any sheet (it's blank) and when I click on the warning (with Centered = checked) it does not move the screen to any location. If I use the command line and type "show NetName1" a box pops up that indicates the net is on sheet x, but when I click on it it just zooms in as far as Eagle supports to the origin of sheet x, and the only thing in this region is the corner of my frame.

As far as I can tell Eagle doesn't understand that the net was deleted because it is part of the design block and somehow that is a conflict? I know it is only a warning but I have multiple identical warnings and would prefer to ensure there is not some invisible net that might affect my board layout (which I have not yet done, I don't even have an associated board yet)

[edwin.robledo]

Hi Nicholas54,

Your continued participation on the forum is greatly appreciated. I sent you a private message.  Can you let me know exactly what version of EAGLE your are using? There were changes done regarding Design Blocks between EAGLE 8.1.1 and 8.2.0.  

From the pull down menu in the schematic, click on Tools/Statistics, let me know if that NET name appears in the Class/Netlist tab. 

Best Regards,

Ed

[Anonymous]

I responded to your private message but you have asked a few more questions so I will post the answers here.

I am using v8.1.1, I tried to upgrade to 8.2.0 but at the time the upgrade links were broken for Windows 64bit and linked to the wrong version so I was not able to upgrade. I made a different thread for this issue and supposedly it is now working but I haven't had time to close all my work and perform an upgrade. Upgrading versions of Eagle is non-trivial because each version seems to introduce new bugs / not well tested before release, and because you have not improved the upgrade process to use a common folder name or allow for in place upgrades. I already have 3 versions of eagle installed and each time I have to manually edit my shortcuts or else risk launching the wrong version. Due to these frustrations and the amount of work I need to get done I haven't have time to try the new version yet.

That all said, when I go to tools > statistics the Class(Signal) tab shows my netlist WITHOUT the nets in question. Also there is a separate area titled "False Nets" which does list the problematic nets in question.

[Anonymous]

So I opened the design block in a simple text editor and found what I believe to be the problem, a few empty net tags with the problematic net names. Can I just delete this section of the file and fix the problem? If yes, how can I fix my project which already build on top of this design block?

I'm guessing now that the problem is when I unselected nets during my design block save process it removed the pieces between the tags but lefts the tags themselves even though they are empty. If this is a solution I could probably avoid this in the future, but am not sure how to fix my existing project. Also, are design blocks treated like parts where I can update a part in a library and can have it update my schematic or is it a one time placement type thing?

[Anonymous]

<net name="NetName1" class="0">
</net>
<net name="NetName2" class="0">
</net>
<net name="NetName3" class="0">
</net>
<net name="NetName4" class="0">
</net>

I forgot to post the code from the design block in my earlier post. It looks like above, you can see that the nets are empty but they are named. These match the ones in my warning (I changed the name to match my example from this thread.

I was able to resolve my project on my own actually through trial and error by placing a temporary fake new net, giving it the same name, it asked me if I wanted to connect the two nets and I said yes, then I deleted the new temporary net and it seems to have deleted the problematic net as well!

Now I'm just looking for confirmation that I can safely manually erase the above code from my design block and I will be all set. Though, someone should make sure that this situation is resolved in the future - maybe it is already resolved with 8.2.0 i'm not sure. As I mentioned in my PM to Edwin, I now believe this problem occurred when I DESELECTED part of my circuit while creating the design block. It seems that deselecting may have removed the items from within my net, but left the empty net named with nothing inside it (see code).

[edwin.robledo]

Hi Nicholas54,

Greatly appreciate providing us your detailed explanation and progress. You can safely remove the code from the Design Block but I strongly recommend you have a reliable backup before editing your source.  I remember running into similar incident many years ago on a board.  They were phantom signals that would appear on reports but had no contribution on the design.  By placing a via or wire with the same name and running ratsnest would get rid of them.   I will try my best to reproduce this error before officially reporting it. 

Just to let you know that EAGLE v8.2.0 does include a Design Block Editor, but I understand if you want to wait before considering upgrading in the middle of a project. 

Best Regards,

Ed

[Anonymous]

I am having the same problem. This started after I tried to copy a small section to a different sheet, and then I went back and deleted the parts and nets from the original sheet. So far I can't figure out how to get rid of it. It does show up in the tool as a "False Net". I was not using design blocks.

Update: I fixed my issue by renaming the original net to the ghost net. The real net was named FEEDBACK. The ghost net was named FEEDBACK1. So I changed the real net to FEEDBACK1 and chose to update all nets on all sheets, then I renamed it back again to FEEDBACK. No error now.

[Anonymous]

I'm glad my posts were able to help you, but sad to see that you ran into this (similar) issue.

I bet it would be helpful to AD if you shared which version of Eagle you were running when you ran into the issue and gave more details about how you go into it. From reading your post it was not clear to me how you reused the circuits between sheets. Did you select a group, make a copy, and then select the copies and use the move tool to drag between sheets?

[Anonymous]

I am using 9.2.2. I have just recently began using more than one sheet and I am finding the process to move parts/circuits from one sheet to a different sheet confusing. I am pretty sure that I used the group command to select the circuit. From there I am not clear how I did it. I have not found any real instructions on how to do it and apparently I found a way to break something.. I wish it were more intuitive, or directions easier to find.

[eur]

Just draw one or more empty nets. Name them like the ghost nets. Check the ERC again, and turn "centered" on. Make sure the ERC points to the new drawn nets.

Delete the new nets. Run ERC again.