New Spice models for multidevice ICs - LM324/2902?

[Anonymous]

I was trying to see if I can draw and simulate some circuits with the quad opamp ICs like LM2902.

Now, the Spice model can be obtained from a good number of places on the web, but when we download the MOD file, change its extension to mdl and maptomodel and choose my mdl file in the dialog, I am greeted with couple of a messages. The last one is the problem. Please see the picture below.

Can somebody please help? I want the simulation on the quad op-amp and not the singular block.

Thanks in advance,

Rahul

[jorge_garcia2]

Hi @Anonymous,

I hope you're doing well. The key here is that you basically have to copy the model 3 times and then add node numbers for the copies. This is the basic gist of it.

I could've sworn we made a video on this. I'll try to dig it up and post once I find it.

Let me know if there's anything else I can do for you.

Best Regards,

[edpataky]

Just a slight correction .. you dont need to copy the model you just need to make a subcircuit model wrapper around the model and instantiate it as many times as devices in the IC (one line each) .. there is an example called “multigate” shipped with eagle that does this .. i will post again shortly with more detail

[edpataky]

OK so here is a little more detail for the solution.  See the "MapMultiGatePart" example under ngspice/Analog/mapgates/ (sorry got the name wrong in previous post) .. open that example and run the simulation command so you can view the netlist .. it looks like this below: 

.SUBCKT LM358D  in1- in1+ out1 in2- in2+ out2 vdd vss
X1 in1+ in1- vdd vss out1 MACROOPAMP
X2 in2+ in2- vdd vss out2 MACROOPAMP
* OPAMP MODEL (LEVEL 2)
* OPAMP MACRO MODEL (INTERMEDIATE LEVEL)
*
*                IN+ IN- VCC  VEE OUT
.SUBCKT MACROOPAMP   1   2   101   102 81
Q1	5 1	7	NPN
Q2	6 2	8	NPN
RC1	101	5	95.49
... more details of model here ... 
.ENDS MACROOPAMP
.ENDS LM358D

Notice that MACROOPAMP is the name of the single opamp model, but LM358D is the multigate part (the IC with multiple opamps) ... The first line of the LM358D model ".SUBCKT LM358D in1- in1+ out1 in2- in2+ out2 vdd vss" has ALL the pins of the IC, and you should do the same for your part.  Then the next two lines (in this case, in your case the next 4 lines) are the instances of the opamps inside the IC which you need to connect to the external pins .. 

X1 in1+ in1- vdd vss out1 MACROOPAMP
X2 in2+ in2- vdd vss out2 MACROOPAMP

So, in your case, simililarly, made a high level subcircuit model wrapper which has all the pins of the IC, then insert the full model inside that subcircuit.  be sure to include lines like above, where you create (identical) instances of the device that you have a model for, and just make sure you connect the pins correctly ... 

So the answer is, for a multi-gate part, you need a multi-gate model .. if you have only a single device model, no problem, that is usually how they come .. just follow the example to create a wrapper to create a full IC model .. then, when you map this model in EAGLE, it will ask you to map each gate of the device to specific model inputs, .. if your model is setup correctly and you map it correctly, it should work just as in the example.  This is admittedly a little more complex than the basic mapping, so if you run into trouble let me know and i can help make sure your model is setup correctly.  

 Note that you must have setup the device in the library as a multi-gate part for this to work .. if any questions on that let me know.  

[sergio.sobrinho1988]

Hello everyone,




Could please help me to create a "Spice model" to an Op-amp with 14 pin (LM324 LT084N). It's my first steps on the Eagle. And I didn't understood very well the explanation. Thank you in advance for the attention.

[edpataky]

No problem i will get back to you later today

[edpataky]

OK ... so this is how you do it:  

Actually there are a couple ways to do this .. one is to make a multi-gate part, so that in your schematic you can place only one gate, or 2 or more .. and you have to place the power pins separately as another gate .. this is useful if you do not want the entire IC symbol in your schematic .. however, i like to sometimes just place the entire IC, and just ground pins that are unused, if any ... it is up to you but the model mapping process is different ... i will use below the simpler case where we place the entire IC symbol and have to connect all pins for simulation to work.  

(1) make a symbol with all the pins of the IC ... go to new Library (or use one you already have) .. make a new symbol first ..  since onsemi has a general spice moodel i will use their datasheet here:  https://www.onsemi.com/pub/Collateral/LM324-D.PDF and model ... for this type of symbol I like to actually draw as it shows in the datasheet, see attached symbol.png.  Make sure to add the special text objects with >NAME and >VALUE in the names and values layers and name the pins properly so you can more easily map the model to the symbol

(2) Click the TOC button (looks like a book) to get back to the library editor, and now add a package ... i will import a package from another library since i know the 14-pin DIP or SOIC exists in many libraries and there is no need to redraw it ... 

(3) In the device editor, add part and add the symbol you just made .. center it on the crosshairs

(4) on the right side of the device editor, click NEW to add a new local package, and choose the imported package, in my case SO14

(5) click CONNECT in the device editor to map the symbol pins to package pins - see the datasheet to make sure it is right - see deviceeditor1.png

(6) once your symbol is connected to the package, now click ADD MODEL and add the spice model.  Choose subcircuit as the type, and load the model ..  model is from here:  https://www.onsemi.com/PowerSolutions/supportDoc.do?type=models&rpn=LM324 .   Now, note that the model is for 1 opamp and we need 4 to make the entire IC .. so just wrap the model with another subcircuit - this means the high level subcircuit line of a model like this, and matching the datahseet should be: 

.SUBCKT LM324_ED OUT1 IN1M IN1P VCC IN2P IN2M OUT2 OUT3 IN3M IN3P VEE IN4P IN4M OUT4 
* subcircuit instances
* existing single opamp model from manufacturer
.ENDS LM324_ED

Now the pin order of the single opamp model we are using has pins given like this in the model notes: 

* PINOUT ORDER +IN -IN +V -V OUT
* PINOUT ORDER 1 2 3 4 5

so when we instantiate each opamp we have to connect the high level pins like IN1P and IN1M to the model properly, connecting to +IN and -IN ... these are actually named with numbers in the model so this is good .. leave as is and connect up everything

see new modified model attached 

(7) In Eagle, choose subcircuit and click MAP - connect the symbol pins to the model inputs

(8) see attached schematic and circuit simulation results

[edpataky]

Posting the images below of the sch and sim results .. also new model here

* BEGIN SPICE MODEL LM324

.SUBCKT LM324_ED OUT1 IN1M IN1P VCC IN2P IN2M OUT2 OUT3 IN3M IN3P VEE IN4P IN4M OUT4 

* have to match order in model below: +IN -IN +V -V OUT
X1 IN1P IN1M VCC VEE OUT1 LM324
X2 IN2P IN2M VCC VEE OUT2 LM324
X3 IN3P IN3M VCC VEE OUT3 LM324
X4 IN4P IN4M VCC VEE OUT4 LM324

* ON SEMICONDUCTOR NEXT GEN MODEL 9/27/2018
* MODEL FEATURES INCLUDE OUTPUT SWING, OUTPUT CURRENT
* THROUGH THE SUPPLY RAILS, CLASS B OUTPUT STAGE, OUTPUT
* SWING, OPEN LOOP GAIN AND PHASE WITH RL AND CL EFFECTS,
* POWER SUPPLY REJECTION WITH FREQUENCY EFFECTS, COMMON
* MODE REJECTION WITH FREQUENCY EFFECTS, INPUT VOLTAGE
* NOISE WITH 1/F, INPUT CURRENT NOISE, INPUT BIAS AND
* OFFSET CURRENT, INPUT COMMON MODE VOLTAGE RANGE, VOS
* WITH TEMPERATURE EFFECTS, AND QUIESCENT CURRENT WITH
* TEMPERATURE EFFECTS.
* MODEL TOTAL SUPPLY VOLTAGE RANGE IS 3 TO 36 V.
* MODEL TEMP RANGE IS -55 TO +125 DEG C.
* NOTE THAT MODEL IS FUNCTIONAL OVER THIS TEMP RANGE
* BUT NOT ALL PARAMETERS TRACK THOSE OF THE REAL PART.
* NOTE THAT LIKE THE REAL PART THERE IS NO AB BIAS
* IN THE OUTPUT STAGE WHICH UNDER SOME CIRCUMSTANCES
* CAUSES HIGH OUTPUT IMPEDANCE AND OR CROSSOVER DELAY
* WHICH CAN EFFECT THE PERFORMANCE IN SOME CIRCUITS.
* THE COMBINATION OF OUTPUT CURRENT SINK AND NO AB
* BIAS WHEN USED WITH A LARGE CLOAD CAN CAUSE SOME
* INTERESTING SMALL SIGNAL STEP OVERSHOOTS THAT ARE
* LARGER THAN NORMAL AND RAMP LINEARLY RATHER THAN
* BEING SHAPED LIKE A CLASSIC OVERSHOOT. THIS HAPPENS
* IDENTICALLY WITH THE REAL PART AND THE MODEL.
*
* PINOUT ORDER +IN -IN +V -V OUT
* PINOUT ORDER  1   2   3  4  5
.SUBCKT LM324 1 2 3 4 5
R44 4 6 4E4
I1 4 7 0.5E-6
Q1 4 8 9 QPI
Q2 4 2 10 QPA
Q3 9 9 11 QPI
Q4 10 10 11 QPI
Q5 12 13 4 QNQ
Q6 13 13 4 QNQ
Q7 4 12 14 QPQ
Q8 3 14 6 QNQ
Q9 15 6 4 QNQ
Q10 3 15 16 QNQ
Q11 3 16 17 QNQ
R67 17 16 4E4
R68 5 17 18
Q12 4 15 5 QPQ
Q13 15 17 5 QNQ
I2 18 3 120E-9
I3 19 3 60E-9
I4 20 3 1E-6
Q14 11 18 3 QPQ
Q15 14 19 3 QPQ
Q16 5 7 4 QNQ
Q17 15 20 3 QPQ
C15 21 22 4.8E-12
R69 12 21 3
R70 12 15 3E9
E2 23 8 3 0 -10E-6
V51 23 1 1.56E-3
I6 3 4 5E-6
R71 4 3 4.5E5
Q18 12 9 11 QPQ
Q19 13 10 11 QPQ
C17 12 13 8E-12
C18 6 15 1E-12
C21 3 24 100E-15
R78 11 24 3E5
C22 1 2 0.23E-12
C23 2 0 0.79E-12
C24 1 0 0.79E-12
E3 22 0 15 0 2
C25 5 0 50E-15
Q20 25 25 0 QNQ
G1 3 4 VT 0 3E-4
I7 0 25 1E-3
V53 25 26 0.25
R79 0 26 1E6
E4 VT 0 27 26 1
R80 0 VT 1E6
V54 27 0 0.55
R81 0 27 1E6
.MODEL QPQ PNP IKF=3E-3 RC=300 KF=4.8E-17 BR=1
.MODEL QPA PNP IKF=3E-3 RC=380 IS=1.01E-16 VAF=245 RE=5 RB=1700 BF=300 KF=4.8E-17 BR=1
.MODEL QPI PNP IKF=3E-3 RC=380 IS=1.01E-16 VAF=290 RE=5 RB=1700 BF=306 KF=4.8E-17 BR=1
.MODEL QNQ NPN IKF=5E-3 RC=25  KF=4.8E-17 BR=1
.ENDS
* END SPICE MODEL LM324

.ENDS LM324_ED

[sergio.sobrinho1988]

I would like to thank you for your fast and excellent support. I never saw a great support like it before. No words to thank you. if not an incovencience. it would be a great idea, if you did a webnair with instruction step by step about how to create a Library (file.lbr) and Model (file.mdl). Don't get me wrong, Your assistence is so good, however there are some coponets that are not on the list of models and library. And I think that is not good, if we ask for your support to every component that we need to implement. With your instruction on the Webnair we will be able to create by ourself, and in case of any doubts we would ask for your assistance. 

[edpataky]

Thank you.  Here is the webinar schedule.  I am hosting one one simulation in about a week and I will make sure to try to hit some of those confusing points.  Thanks again

http://eagle.autodesk.com/eagle/events