impedance calculation in Eagle

impedance calculation in Eagle

Anonymous
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Message 1 of 8

impedance calculation in Eagle

Anonymous
Not applicable

Hello Team 

 

I am Anuradha, using EAGLE 8.3 premier version

I want to know that Can I calculate impedance  of differential pairs (traces) in pcb layout 

 

Thanks 

Anuradha

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13,342 Views
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Message 2 of 8

jorge_garcia
Autodesk
Autodesk
Hello @Anonymous,

I hope you're doing well. EAGLE doesn't currently have a built-in impedance calculator so you will have to use third-part tools to be able to make the calculations. Go ahead and google the Saturn PCB toolkit for a good useable calculator.

Let me know if there's anything else I can do for you.

Best Regards,


​Jorge Garcia
​Product Support Specialist for Fusion 360 and EAGLE

Kudos are much appreciated if the information I have shared is helpful to you and/or others.

Did this resolve your issue? Please accept it "As a Solution" so others may benefit from it.
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Message 3 of 8

Anonymous
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How can Eagle lay out differential PCB tracks then, when it doesn't know nothing about the impedance?
It's only logical then that the impedance will fluctuate over the bends! (not to mention the effect of copper under the traces!
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Message 4 of 8

rachaelATWH4
Mentor
Mentor
Accepted solution

@Anonymous wrote:
How can Eagle lay out differential PCB tracks then, when it doesn't know nothing about the impedance?
It's only logical then that the impedance will fluctuate over the bends! (not to mention the effect of copper under the traces!

You use an external tool (there are many available via Google) and calculate your PCB stack-up and trace width/gap for your diff pairs. Then you set up your DRC and a net class for the diff pairs in EAGLE and apply the net classes to nets with _N and _P suffixes so they become diff pairs. Now when you route the diff pairs they will route as specified, and the trace/gap settings are enforced as you route. It's not perfect but it works, so long as you keep your diff pairs to a single layer with a solid plane next to them (which you'll have specified in the calculator you used).

 

I do agree that EAGLE should be able to calculate these parameters though, and there are other short comings which make some things problematic. For example, if you need to change layers then the impedance matching parameters will likely change, and the net classes can't deal with different layers. If you could just specify the impedance in the net class and it work it out on the fly as you were routing that would be the optimal solution.

 

Best Regards,

 

Rachael

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Message 5 of 8

Anonymous
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yes, yes, but first, PAD shape recognition as a part of the trace.
Eagle always tries a wrong way out of a pad.

Symmetric bends are more complicated than a circular shape, Bezier is needed, but Eagle can't do even a circular circle at the moment!

DROPLET inlets and exits would be welcome for the mechanics and signal integrity at the same time! (In non-diff signals as well)
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Message 6 of 8

csvanberg
Advocate
Advocate

"DROPLET inlets and exits would be welcome..."

 

I'm not sure if you mean "teardrops"? There is a ULP included for this.

Once applied, however, they are not easy to move so I apply the script after the board layout is finished. Save a version if you need to make changes.

 

I have looked at the impedance numbers from at least four different impedance calc software sources, they all come up with different numbers fo CPW-ground.

IPC standards are the base for the excellent Saturn PCB. (Linux version does not runs under Wine as intended).

 

Mantaro and HughesCircuits comes up with very different results for "asymmetric stripline", in my case 49.7 ohms vs. 67.9 Ohms, respectively. I think the latter is really off.

 

What is not included in these calculator inputs is the effect of soldermask. Most likely, the programs assume no soldermask, but that is a guess.

One way around this would be to use "Embedded Microstrip" calculation, and place the trace ~ 2 mil under the surface. This would assume the same dielectic constant for both the soldermask and the board material.

 

For very low loss/high power/high frequency work I would leave the trace, and its sides if CPW, bare.

 

Constant impedance bends would typically imply mitered corners. With differential pairs this gets complicated. If the radius of a bend  is more than three times its width, impedance should be constant.

This would be the easiest way, if you don't have room for this then some stronger medicine is needed.

 

 

 

 

 

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Message 7 of 8

csvanberg
Advocate
Advocate

"...Eagle always tries a wrong way out of a pad...."

 

Agreed, there should be some smarter way to deal with this, possibly if Live DRC is set to "on" at least it should respect not getting too close.

For sure you do not want traces too close.

Now you have to start with a trace right out of the pad, click-stop, and then do your bends, size changes etc.

Digital layout can now be high enough frequency to be treated as RF circuits. 

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Message 8 of 8

matt.berggren
Alumni
Alumni
Thanks guys! This is something we’ll look at. There are some pretty interesting things we can do here to help improve the pad entry/exit and teardropping.

Best regards,

Matt - Autodesk
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