How to Design PCB Stencil to Optimize Solder Paste Uses?
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For QFN and other SMD IC packages
For other RLC SMD pacakges
Hello all,
I am using Eagle to design my PCBs. For the last few months, I have been designing mostly with SMD components and I have realized that due to the design of the stencil, I am putting way too much solder paste on the PCB board. I have seen many stencil designs where other than spreading the paste on the whole pad of the component (even for resistors and capacitors), it is spread on some sections of the pad by cutting the stencil in different patterns (reference image added above).
To do something like that do I need to prepare the stencil layer (is it "tCream" or "tPlace" layer?) by myself and send it to the PCB fabrication house or do I need to request the PCB fabrication house to do it for me?
If I need to do that by myself then I would appreciate it if someone can share the knowledge of how to make that kind of modification on the "Stencil layer" in Eagle. And if I need to request the PCB fab house then what technical term should I use to let them know that I need that feature on the stencil?
Thank you all.
