Help with Via In Pads

[Anonymous]

I an new to Eagle and having issues with via-in-pads. I placed the via in the pad of my SMD component. The pad is connected to my +DC net on the top side of the board. I have placed a polygon with the same net name on the bottom side of the board. To connect the +DC pad, I placed a via in the pad of SMD component. I expected it to automatically detect that I was placing a via-in-pad and connect the via to the appropriate net by default. This did not happen; it named the via with the next available net name that was unused. I manually changed the via name to the the appropriate net name but when running the DRC it shows that it is still not connected. 

Is there a way to set it up so the net names becomes that of the pad/polygon when placed in one? How do I connect this pad/via/polygon correctly using a via-in-pad?

Your help is appreciated.

[m3atwad]

I have struggled with this as well regarding vias in thermal pads.

[Anonymous]

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@m3atwad wrote:

I have struggled with this as well regarding vias in thermal pads.

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To remove the thermals, just to to the polygon properties and uncheck the option for thermals.

[m3atwad]

Well, my issue isnt thermal relief geometry. I want to embed vias in the
thermal ground pad.

For some reason placing vias on top of the pad seems to yield an airwire I
cant get rid of.

[Anonymous]

O ok I see. I still have't figured this out. If you do, will you either post a link to the solution or let me know how to? I'll do the same if nobody else helps first.

[jorge_garcia]

Hi Guys,

I hope you're doing well. There are a few ways to do these. I'll mention the one I prefer. In the library, add through hole pads that will serve as thermal vias. Surround them in a polygon on the top layer(you do not need an SMD on the top), make sure to repeat the polygon on the tStop layer so you get the stop mask opening. In the device editor connect all of those pads to the same pin.

Because of the arbitrary pad shape feature EAGLE will see the polygon as an extension of those pads. The main benefit here is that you only ever have to do this once. You may still get some DRC errors, but this is the best way I have found.

Let me know if there's anything else I can do for you.

Best Regards,

[Anonymous]

For my situation, this solution does not make sense. I am using 2220 package capacitors from the built in Eagle library. I would like to know how to solve the problem by simply placing a via and having it connect to the net that it should connect to. I do not want to have to copy an Eagle part so I can edit it, or create my own. There are a few reasons this would not be the optimal solution. I may want to change the via sizes in future boards. I would have to edit the part. I may want to add additional vias, or remove some. This again would require me to copy the part or edit the existing part. So if you have a way to just add the via in pad and have it connect to the correct net like other PCB layout programs, that would be ideal.

[m3atwad]

Hi Jorge!

I will try it the way you recommended I have never done that.  I think where I went wrong was using the SM pad rather than the polygon.  

I would agree with @Anonymous that a fair request is for eagle to be smart enough to figure out how to connect a via to another copper geometry with the same net.  This is pretty common in other ECAD packages.

Jorge correct me if I'm wrong, but I believe currently you can place vias in another copper geometry and even though the DRC gets mad you can still fabricate and receive a valid connection.  You should be able to verify this with the gerbers as well since the vias will show up as connected or not to pad or copper geometry in the gerber files.

[Anonymous]

I have came to the conclusion that it is an issue with Eagle being a not so great ECAD program. From what I'm witnessing so far, vias do not automatically get connected to the copper they are placed on like other programs. This is a huge inconvenience and makes no sense. If you place a via on a specific pad or trace, you more than likely want it connected to it. If you do not, change it manually. I'd be willing to be that more times than not you would not be changing it though. Also, there is no way to directly export ODB++ files. Why is this? What if I want to do further analysis such as E-field analysis, parasitic extraction, current density analysis, thermal analysis, etc.? Well, I guess I just have to figure that out on my own. And those are not just hypotheticals because I do want to. Anyway, you get what you pay for I guess. Some of the time anyway. I hope Autodesk gets this figured out soon. 

O and for the record, I was able to verify that the vias are in the pad and connected, even though Eagle says they are not. Airwires and a DRC check are pointless if they're mean nothing. With that being said, for anyone else having this issue, don't trust Eagle because you may actually be just fine. And if there is some way to correct this problem THE RIGHT WAY, I'm hoping someone will tell me because editing a footprint to already include them is a band-aid for an actual problem and makes no sense in most situations. 

[m3atwad]

I share a lot of the same frustration.  I will say they have come a long way - I've been a user for quite some time.  It is hard though when you run into fundamental problems like this.  Especially when you have previous experience with more mature ECAD like mentor or Altium.

I think the biggest problem the team has (and I've felt this way for a long time) is that there is no one on the eagle team actually designing complex boards with eagle.  I think they (the eagle team and the devs) would learn a lot if they would just hire (or assign) an EE to design a 14 layer high speed mixed signal board.  Or even just a high speed digital PCB with 14 layers or so.  Use a big SoC like a big zynq or zynq ultra scale, big power system and multi gig high speed transmission lines etc...  

I think if they had someone on their team that started from scratch and took the design to fab (BOM, drawings, fab notes etc..) they would develop a giant list of action items and a lot would be these details that are very fundamental and very important.  The support guys on here are really good, but Autodesk will never produce a high quality ECAD product without going through multiple exercises like this.  Thats my 2 cents anyways...

[Anonymous]

I totally agree .