can't get rid of overlap errors

[johnsmythwithawye]

1. using the wire method, I routed a wire and manually placed a via between the bottom and top layers.

Now I am getting an overlap error.

2. Another instance, using the route method routing the top layer trace, then switching to bottom layer (EAGLE automatically puts a via here) now i am getting an overlap error. 

I've ripped up and re-ran the tracks but the errors still appear.

Shouldn't the top track be overlapping the bottom track inside the via? I tried to shorten the tracks so they don't overlap (even though they are on separate layers) but it does not help, overlap error still shows.

I have searched for a solution but never seem to find a straight answer. I have attached a picture.

Any help is greatly appreciated.

Greetings from Canada!Overlap Error

[one-of-the-robs]

First off, have you cleared all the errors and re-run the DRC? They could be left over from before you changed things.

If that's not it, do you perhaps have two vias there? When you added on by hand, did you make sure to name it for the correct net?

[johnsmythwithawye]

Thanks for responding. Yes I have cleared the errors. I have to exit Eagle, then restart it. Another DRC check reveals the same errors. The errors won't appear again if they are cleared, but once eagle has been restarted, the errors come back. There are not two vias there, I am sure of it.

I managed to fix two of the other vias by disabling all layers except the vias, then it would allow me to name the via to match the net. So these problems are fixed.

There is one I cannot figure out. Two tracks are joined in a pad. I checked, and there is no via inside the pad,

NO MATTER WHAT I try to do, I am getting  the overlap error and clearance error. (see picture below).

I thought that since there is a top layer track joining a bottom layer track this would be a problem, but i tried changing to two top layer tracks, then two bottom layer tracks (going to the pad in the picture) but nothing changes, still those errors!

I don't see a problem, I am hoping to find a solution as I have never figured this out when using Eagle.

[one-of-the-robs]

So that we know the context, how are you placing those traces? Do you have a full schematic that is simultaneously open and free of any ERC "consistency" errors? And if you rip up the problematic traces, do the resultant airwires go to that pin?

[johnsmythwithawye]

I have a proper schematic that is open and free of any errors. There are 4 warnings that I approved.

These have to do with the same problem (overlap, clearance error) in the board file (see the picture in my post above).

I placed the tracks on the schematic by selecting NET. On the PCB, I place the tracks by selecting Route.

When I ripup the tracks on the board, the airwires go to that pin.

I have ripped up that section (in fact all wires going to that pin) and re-did them. Still the same errors.

I have had this problem with other boards before, I just never figured out why or how to fix it.

And I don't have days or weeks to waste so I usually just give up and submit the board with the errors.

So far i have never had any trouble, but it would be nice to know WHY this is happening.

Thank you

[one-of-the-robs]

Would it be possible to upload the design here? We can figure out a lot more by seeing the real design rather than just screen shots.

Also, is the pin in question part of a standard library device or from a third-party or custom library?

[johnsmythwithawye]

Sorry i can't upload the design. Thanks a lot for offering to help.

I am not overly concerned because this happens to all of my boards when using Eagle,

I just approve them every time.

In this board file the errors appear on one of the pins in a 3 pin thru hole header.

The 3 pin header is from Sparkfun-Connectors library.

1x03, 455-1750-1-ND

is all the information I can find in the properties menu.

thanks again.