Hi
we have successfully designed a few complicated and some simpler boards while using EAGLE 6.60 Professional. Now we had a fairly simple cpu board and noted that it is not working. It took a while to recognize that two wires are not routed by the Autorouter. Also the statistics does not indicate anything missing.
The netlist is OK and so is the schematics. Two chip pins are totally ignored. The same kind of logic chip is used onboard already so it is not a footprint error. If one wishes to manually route it, it is not possible since the router sees the board as completed. If one tries to use the Autorouter to complete the two missing wires, there is nothing to do. One can manually force routing by using named wires and thus complete the wiring.
I think this error is alarming. I ask the manufacturer to quickly upgrade with the bug removed, the older version V6.60 included. We have no plans of going to higher versions at this time. I can supply the design files for troubleshooting.
Hi
Now that everything has been checked and rechecked a few times I can see that we were wrong. Sorry for this.
There is a minor gap in the schematics wiring disguising the fact that there is actually no connection. Also the netlist was reflecting it properly.
Sorry guys!
Hi
the original mistake was ours by leaving a small gap in the wiring.
However, EAGLE does not warn of this in the warning list. These two chip pins are not in the warning list, all others are. We would absolutely have detected this fault if it were. This IS a bug in EAGLE.
Henrik
Hi Jorge
and thanks for your assistance.
We always use the ratsnest etc. to finalize the design.
The problem this time was not the pcb itself but the schematics. We had accidentally left two small gaps between the wires to pins. It was easy to ignore it. And this will lead to the final problem.
However, the half of the problem is from the EAGLE's schematic editors checking utility. It does not recognize these empty pins although it will report other unused pins. So, in my mind there is some bug in this facility. Otherwise we could have observed the error already in the schematics phase as we always go through the warnings.
Best regards, Henrik Stenlund