About staggered vias and full stacked vias.

[aa4649]

I make a very small board.
Build up two layers at a double-sided board (2 + 2 + 2).

staggered vias and full stacked vias

However, EAGLE can not set layer properly.

EAGLE can create IVH between 1-2, 8-9, 15-16,
EAGLE can not create IVH between 2-8 and 9-15.
Also, it is not possible to set each IVH to switch to staggered / full stacked.

I increased the connection as much as possible.

[rachaelATWH4]

Hello,

I appreciate this is a couple of months old but I remembered you'd posted it so thought I would come back to you now as I have just had a very head scratchy day with a dense microvia board I am working on and I have had to work out how to do staggered/stacked vias.

So in your second example in your DRC layer setup I believe you should have something like:

[2:(1+[8:(2+8*9+15):9]+16):15]

This will define a blind via for the stack up between layers 2 and 8 and again between layers 9 and 15. You can then place these either staggered or stacked in your design I think.

I'm still working through the design with this technique in so I may yet come unstuck here. Does anybody else have any thoughts on this?

Many thanks,

Rachael

[ADresden]

Hi Rachael, glad your brought this up!

The layer definition needs also the ability to define vias and via types, their fill, etc. Currently, eagle can't produce oblong PTH holes, only via 100 workarounds, and it has no glue about IPC via types, their filling, etc.

Board houses then also can't define their rules or options in eagle.

I think the whole definition should also be a point-and-click process and not typing magic into a command line.


P.S. My designs can't afford micro vias or conductive filled vias, I'm chasing the cost.

[aa4649]

Hello everyone,
I write a memorandum after trial and error.

Type A
Layer_6_1_4_1_BH015035_Laser01025_0127.dru
[2:(1+(2+8*9+15)+16):15]

Type B
Layer_6_2_2_2_FullStack015035_Laser01025_0127.dru
[15:[9:[8:[2:(1+[8:(2+(8*9)+15):9]+16):15]:9]:8]:2]

 

Type B is still incomplete.
I noticed that in EAGLE, only buried holes VIA 1-2, VIA 15-16 are "Miro Via", and other buried holes and through holes are "VIA".

The "Min. Micro Via = 0.1 mm" rule seems to apply only to VIAs 1-2,15-16.
For all other VIAs 1-8, 1-9, ... the "Minimum Drill = 0.15 mm" rule applies.

If I designed in the case of a 2-2-2 full stack layer configuration, the center 8-9 buried holes and 1-16 through holes are "VIA". Other holes (1-2, 2-8, 9-15, 15-16,.. and so on) should be "Micro VIA". But in current EAGLE it can not be set like that.

Attach the DRC file used for the test.

[aa4649]

Maybe this is the most combination layer composition?

Type B2
Layer_6_2_2_2_FullStack015035_Laser01025_0127.dru
[15:[9:[8:[2:(1+[9:[8:(2+(8*9)+15):9]:8]+16):15]:9]:8]:2]

Board manufacturers would say they want their drill data out with the lowest common denominator.
(For example, drill data output per 1-2, 2-8, 8-9, 9-15, 15-16)
It would be nice to have such a job script (current "excellon.cam" possible?)

[rachaelATWH4]

---

@aa4649 wrote:

I noticed that in EAGLE, only buried holes VIA 1-2, VIA 15-16 are "Miro Via", and other buried holes and through holes are "VIA".

The "Min. Micro Via = 0.1 mm" rule seems to apply only to VIAs 1-2,15-16.

---

I'm not sure this is correct. I have a board with stacked microvias and it appears to be taking the minimum microvia drill size for my 2-3 vias correctly as I am not getting any DRC errors about them.

---

@aa4649 wrote:
Board manufacturers would say they want their drill data out with the lowest common denominator.
(For example, drill data output per 1-2, 2-8, 8-9, 9-15, 15-16)
It would be nice to have such a job script (current "excellon.cam" possible?)

---

With my current configuration for my 10-layer microvia board this is exactly what I am getting.

Configuration string:

[2:(1+[3:(2+3*4+5*6+7*8+9):8]+16):9]

Output Files:

<brdname>.drd.0116
<brdname>.drd.0102
<brdname>.drd.0203
<brdname>.drd.0209
<brdname>.drd.0916

Note: There is no file for 0809 as I don't have any vias between those layers. I.e. it generates them only for used via types.

Best Regards,

Rachael

[aa4649]

I have created Staggered VIA.

Type C
Layer_6_2_2_2_Staggered015035_Laser01025_0127.dru
[2:(1+[8:2+(8*9)+15:9]+16):15]