Simulation in EAGLE is going Digital!

[edwin.robledo]

Simulation in EAGLE is going Digital! Join EAGLE Desktop Product Owner ED Pataky on Thurs 9/27@ 5PM EDT for a Sneak Peak Webinar to find out about the coming new Analog and Digital Simulation features! Register now! 

[engineeringNCMXB]

Thursday, September 29th?

[jorge_garcia]

Hi @engineeringNCMXB,

I hope you're doing well. That is correct sir, the webinar is today September 27th at 5PM EDT.

Please let me know if there's anything else I can do for you.

Best Regards,

[crrrack]

Today is the 27th...

[jorge_garcia]

Hi @crrrack,

That's what I said... just kidding I edited my post to reflect the correct day. The picture has the date wrong, but the text has it right. The webinar is today.

Sorry about the confusion.

Best Regards,

[rg.jones]

Hi Jorge, was it recorded?

[jorge_garcia]

Hi @rg.jones,

I hope you're doing well. It was recorded and should be posted shortly.

Let me know if there's anything else I can do for you.

Best Regards,

[banksysan]

@edwin.robledo  Was this recorded?  If it was, is it still available?

[RichardHammerl]

Hi @banksysan 

there is a recording on our youtube EAGLE channel: https://youtu.be/BCpYbKRfPa4 

I hope this helps.

Best regards,

[banksysan]

Ah.  My Googling found that one.  I've followed it along but it skips past the first step, how to create a new digital/analogue circuit in the first place.

In my schema, as soon as I put a digital component and a convertor the simulation never finishes.  Could you do a video on just creating a functioning digital/analogue circuit from a new, blank schema?

[jorge_garcia]

Hi @banksysan ,

Do you have a schematic you could share of what you are trying to do? It's possible you did everything correctly but if the simulation isn't setup just so you might not get it to converge. In this respect our current implementation is temperamental.

Let me know if there's anything else I can do for you.

Best Regards,

[banksysan]

Thanks.

I've got a video:

Here's the Netlist and a screenshot too:

* SpiceNetList
* 
* Exported from untitled.sch at 21/09/2021 13:29
* 
* EAGLE Version 9.6.2 Copyright (c) 1988-2020 Autodesk, Inc.
* 
.TEMP=25.0

* --------- .OPTIONS ---------
.OPTIONS ABSTOL=1e-12 GMIN=1e-12 PIVREL=1e-3 ITL1=100 ITL2=50 PIVTOL=1e-13 RELTOL=1e-3 VNTOL=1e-6 CHGTOL=1e-15 ITL4=10 METHOD=TRAP SRCSTEPS=0 TRTOL=7 NODE

* --------- .PARAMS ---------

* --------- devices ---------
X_X2 N_1 DRIVERD1_1 
X_X1 N_1 N_2 ATODB 
R_R1 N_2 0 1 

X_D1 N_1 DIG_N_1 DTOAB1
* --------- models ---------

* model file: Base: C:/Users/banks/Documents/EAGLE/projects/Digital Circuit/DigitalAnalogue/DRIVERD1.mdl, DRIVERD1_1

**********************
* autodesk eagle - spice model file
**********************
.SUBCKT DRIVERD1_1 n1
a_source [n1] d_source1
.model d_source1 d_source (input_file="C:/Users/banks/Documents/EAGLE/projects/Digital Circuit/DigitalAnalogue/driverd1_1.dsource.txt")
.ENDS DRIVERD1_1


* (model found in library)

**********************
* Autodesk EAGLE - SPICE Model File
**********************
.SUBCKT ATODB A D
abridge [A] [D] adc_buff
.model adc_buff adc_bridge(in_low = 0.3 in_high = 2.5)
.ENDS ATODB


**********************
* Autodesk EAGLE - SPICE Model File
**********************
.SUBCKT DTOAB1 D A
abridge [D] [A] dac_buff
 .model dac_buff dac_bridge(out_low = 0.3 out_high = 2.5)
.ENDS DTOAB1

* --------- simulation ---------


.control
set filetype=ascii
TRAN 0.03 6 0 0.03 
write untitled.sch.sim V(DIG_N_1)
.endc

.END

[holger.vogt]

There is a bug in your circuit.

out from X2 is digital.

You then select the A->D converter. It has to be a D->A converter.

[banksysan]

You're correct.  Sorry, typo from looking at this for too long.

I've corrected that and get the same problem,.

* SpiceNetList
* 
* Exported from AnalogueDigital.sch at 22/09/2021 17:41
* 
* EAGLE Version 9.6.2 Copyright (c) 1988-2020 Autodesk, Inc.
* 
.TEMP=25.0

* --------- .OPTIONS ---------
.OPTIONS ABSTOL=1e-12 GMIN=1e-12 PIVREL=1e-3 ITL1=100 ITL2=50 PIVTOL=1e-13 RELTOL=1e-3 VNTOL=1e-6 CHGTOL=1e-15 ITL4=10 METHOD=TRAP SRCSTEPS=0 TRTOL=7 NODE

* --------- .PARAMS ---------

* --------- devices ---------
X_X1 N_1 DRIVERD1_1 
R_R1 N_2 0 1 
X_X2 N_1 N_2 DTOAB 

X_D1 N_1 DIG_N_1 DTOAB1
* --------- models ---------

* model file: Base: C:/Users/banks/Documents/EAGLE/projects/Digital Circuit/DigitalAnalogue/DRIVERD1.mdl, DRIVERD1_1

**********************
* autodesk eagle - spice model file
**********************
.SUBCKT DRIVERD1_1 n1
a_source [n1] d_source1
.model d_source1 d_source (input_file="C:/Users/banks/Documents/EAGLE/projects/Digital Circuit/DigitalAnalogue/driverd1_1.dsource.txt")
.ENDS DRIVERD1_1


* (model found in library)

**********************
* Autodesk EAGLE - SPICE Model File
**********************
.SUBCKT DTOAB D A
abridge [D] [A] dac_buff
.model dac_buff dac_bridge(out_low = 0.3 out_high = 2.5)
.ENDS DTOAB


**********************
* Autodesk EAGLE - SPICE Model File
**********************
.SUBCKT DTOAB1 D A
abridge [D] [A] dac_buff
 .model dac_buff dac_bridge(out_low = 0.3 out_high = 2.5)
.ENDS DTOAB1

* --------- simulation ---------


.control
set filetype=ascii
TRAN 0.025 5 0 6 
write AnalogueDigital.sch.sim V(DIG_N_1)
.endc

.END

[holger.vogt]

Please post the contents of
driverd1_1.dsource.txt

[banksysan]

Where would I find that? I only have two files, the .sch and .sch.net.

[jorge_garcia]

Hi @banksysan, 

You can find the models for the built in parts in the EAGLE installation directory, inside of examples > spice > examples.

Let me know if there's anything else I can do for you.

Best Regards,

[banksysan]

Found it.

0 0s
20m 1s
25m 0s
40m 1s
45m 0s

[banksysan]

Actually, I have several.  I think this is the effective one though:

0 1s
1 0s
2 1s
3 0s
4 1s
5 0s

[banksysan]

Thanks @jorge_garcia, I'm using the ng-spice libraries and have have the models assigned (I'd get an error if I tried to simulate without those).