How to define NPTH in two layer PCB?

[bhairavi1705]

Hello everyone,

   I am using Eagle 8.0.1 as a hobbyist. I have designed a two layer PCB.

   And  now requirement is that all components PADS to be NPTH (Non Printed Through Holes) and VIAS are to be PTH before starting auto route in Eagle.

  Is there anyway  possible  to make all Components PADs NTPH in eagle for multilayer (or 2 layer) PCB?
  Can anyone help me, please?

Thanks & Regards

[jorge_garcia]

Hi @bhairavi1705,

I hope you're doing well. Where is this requirement coming from? Having pads not be plated through means the top and bottom sides of the via do not connect. This could lead to non-functioning boards and I can't think of a good reason to do something like that.

Let me know if there's anything else I can do for you.

Best Regards,

[bhairavi1705]

Hi Jorge Garcia, 

   Thanks a lot for replying. 

   I am doing fine and hope the same from your side too. 

   Where is this requirement coming from?

   As a hobbyist able to make  single sided pcb at home and  unable to make double sided pcb (as required complex process for PTH). 

   And this design is a little complex to fit only in the bottom route and having little more  unrouted tracks (so many jumpers).  

   Hence plan to route all jumpers (unrouted tracks) manually on the top layer using VIAS . 

   So during soldering I know only have to solder VIAS properly and all components PADs are solder as single sided.(as all components PADs are difficult to solder on both side)

  Requesting if possible to do the same (that is PADs as NPTH & VIAS as PTH)  please let me know. 

  Please let me know if you need any more details on the same. 

 Thanks & Regards

[jorge_garcia]

Hi @bhairavi1705,

I hope you're doing well. Since you are home etching then you don't have to worry about defining the pads as NPTH, since you can't reproduce the plating anyway. 

Route it with the default configuration and then just etch your board like normal. you'll have some extra copper around the pads but it won't affect the performance of the board.

Let me know if there's anything else I can do for you.

Best Regards,

[bhairavi1705]

Hi Jorge Garcia,

Thanks for Replying .

It seems  you are assuming I am using SMD components but not using SMD components. 

So if PADs are PTH then at top level during auto route, tracks are routed from Top component PADs assuming Top and Bottom PADs are in contact as PTH  but that is not the case with me when etched PCB. 

For example if used IC socket then IC socket pins are connected at bottom PADs as doing soldering on bottom side.

And in my case top component PADs are not in contact with  either Bottom PADs (as not PTH)  or IC socket pins (as will not be able to do solder for many components pins on top side as non SMD components) .

And if tracks are routed through TOP pads then that breaks functionality.

That is why if Components PADs are not PTH (NPTH) then during auto route at top level,  tracks are not created from top PADs and only routed through VIAS. 

Please let me know if I am missing anything . 

Thanks & Regards

[jorge_garcia]

Hi @bhairavi1705,

I understand you are not using surface mount devices. In essence, you want to do a single layer PCB.  So here is the trick and let me know if it's not clear. For this explanation, I'm going to assume that all of your components mount on the top of the board and the leads go to the bottom where you will solder them. So all of the soldering happens on the bottom of the board.

In this situation, when you run the autorouter most of the routing will happen on the bottom of the board. You can adjust the cost factors to favor the bottom. You can add restrict areas on the top layer around the components to make sure they connect on the bottom. This will make sure that any routing that happens on the top layer will be between vias. Any traces on the top will be replaced by wire jumpers on your finished PCB.

This really simplifies making the single layer PCB and allows you to leverage the autorouter.

Let me know if there's anything else I can do for you.

Best Regards,

[bhairavi1705]

Hi jorge.garcia,

Thanks for providing solutions/suggestions for the same. 

Your solutions of

1) Adjusting cost factor (attaching as "Cost_factor_top_99.png")

2) Add restrict areas on the top layer around the components (doing by drawing cut-off polygon and as small as IC Pads attaching as "Restric_by_polygon.png")  

   seems fine for  problems.

But still some top components PADs are routed  (attached as "Top_Components_Pads_Routed.png") .
And above might be (as not analysed) routing is not possible at bottom & hence the only option left is Top.

  Anyhow, doing some more experiments to get expected/better results.

  But please can you confirm that (by observing the attached snapshot) , what I am setting/doing for Adjusting cost factor & Add restrict areas is correct or not ?

Thanks & Regards

[jorge_garcia]

Hi @bhairavi1705,

I hope you're doing well.  So a couple of points, for the Cost factor make sure that in all of the tabs you set the cost factor for top to 99. For the restricts you draw on the tRestrict layer not Top. Everything tRestrict covers is a no go area for the autorouter. So if you want, draw a rectangle on the tRestrict layer covering the pads. That will guarantee that the autorouter won't connect to the pads on the top layer.

You are getting there.

Let me know if there's anything else I can do for you.

Best Regards,

Jorge Garcia 

[bhairavi1705]

Hi Jorge Garcia,

Thanks a lot for the reply & help . 

Suggestion 1:  for the Cost factor make sure that in all of the tabs you set the cost factor for top to 99.

Yes I was doing for all tabs that are "Route & Optimize1 ,2 ,3 & 4" . 

And also for all 5 Routing Variants (as selected effort low) so I can select the best out of 5. 

Attaching snip : "Routing_info.PNG"

Suggestion 2:  For the restricts you draw on the tRestrict layer not Top.

Yes above was a mistake and then understood that tRestrict is  Nogo areas for top side tracks.

Attaching working snip after route as "tRestrict.png" 

I have seen that after this experiment number of VIAS increase drastically ("Routing_info.PNG") 

But fine,  I can now play around with tRestrict area and balance VIAS and tRestric based on board feasibility.    

Thanks again for your help in solving the issue. 

Regards. 

[jorge_garcia]

Hi @bhairavi1705,

I hope you're doing well. That looks great.

Happy that it's working better for you. One thing I'll mention, if the board is relatively simple you will usually get a better result if you route the boards manually. It's a good skill to develop and you'll find that usually you can produce a more aesthetically pleasing routing result.

Best Regards,

[bhairavi1705 · Accepted solution]

Hi Jorge Garcia,

   Yes you are right .

   Actually the design is a little complex & already divided the schematic into 3 parts with connectors so it can fit into a 6x4 inch home PCB board and can be done  changes and experiments.

   And one of BRD created as single sided and routed Manually for all untracks and etched also.

   But it's a little hectic so thinking of using tool to reduce the efforts for the other two. 

   And did a further few more experiments and got better results (VIAS also reduced to less than 100). 

   Thanks again for help.

  Thanks and Regards