Best practice to connect two nets together with short on footprint

Best practice to connect two nets together with short on footprint

4ckatro
Enthusiast Enthusiast
910 Views
3 Replies
Message 1 of 4

Best practice to connect two nets together with short on footprint

4ckatro
Enthusiast
Enthusiast

Hello!

 

For prototyping it is a really good practice to put small copper shorts for each pin of a microcontroller like this:

4ckatro_0-1635138140783.png

4ckatro_1-1635138215547.png

 

I created a two pin device, where the two pins are connected together on the footprint:

4ckatro_2-1635138413015.png

 

If the wiring of the pins are messed up during design, still there is a chance to fix the prototype with copper cuts and air-wires.

 

However with this technic tons of DRC overlap error appears in the design. If I have two device with ~200 pins I got ~500 DRC overlap error and it is really annoying, hard to check each of the error.

 

Is there anyway to tell EAGLE to not check overlap DRC on a specific footprint?

 

Or is there any better way to do this?

Reply
Reply
0 Likes
911 Views
3 Replies
Replies (3)
Message 2 of 4

one-of-the-robs
Advisor
Advisor

The standard answer is the "approve" all the DRC errors, which is fine for a single star earth point but not for every pin of a micro.

An alternative would be to draw the link on a user-defined (non-copper) layer, then export that layer as part of the top copper Gerber. This means the link is invisible to the DRC but gets included on the real board. It's a bit of a hack, though, and risks coaster making if anything else ends up on that layer. Also, custom CAM jobs, which some people find awkward.

Reply
Reply
0 Likes
Message 3 of 4

4ckatro
Enthusiast
Enthusiast

Thanks for the reply. The only problem with non copper layer is the polygon pour like GND which fills the board. If I do not have a copper between the pads the polygon pour could fill it. But of course I can trick it with small enough space to not fill copper between the pads... And still it can cause errors, if I forgot to export that layer as a copper layer or the pcb manufacturer do not merge the two layers I will be in trouble. It would be really nice if I could solve it on the footprint. But I afraid Eagle is not capable to do this.

For approve all DRC it is not a ok, because probably there are some real error what I would like to find out from the DRC check. 

Reply
Reply
0 Likes
Message 4 of 4

one-of-the-robs
Advisor
Advisor

You can prevent the flood fill issue by placing a "tRestrict" or "tKeepout" (I never remember which is which so check the manual!) rectangle on the footprint.

Reply
Reply