@dougmcalexander wrote:
That would indicate the existance of a WD_M block that has WIRE* in the list of layers to treat as a wire. If you ever used the utility to update your library WD_M block from the one in your drawing, then the stock WD_M could contain the values from your drawing that are causing problems, tus perpetuating the problem.
Remember, I saw two WD_M blocks in your drawing, one nested and one not. You might have to use ATTMODE=2 to view the WD_M block and be sure that WIRE* is not in the list of layers to be treated as a wire.
Note that WIRES* is a valid entry in the list because the default wire layer that the software uses is WIRES. Don't delete WIRES*, only delete WIRE*. So open the library that your project is pointed to and check the WD_M.dwg file to be sure that the list doesn't include WIRE*. Then when you insert this block into a fresh drawing it will not cause problems. In fact, here is a better idea. Tell me which library you are using and I will send you a fresh WD_M.dwg file to replace yours, in case yours has been altered.
Okay, something's still hinky.
I went back through and literally recreated everything from scratch using your method, and while I no longer have issues with the wire number layers getting made into actual wire layers, I do have a new issue.
Once I got it all finished, I created a new drawing using the new template file. Just to be sure, I went in and set ATTMODE to 2 to see what the wire numbers are. Everything was perfectly in place, and this is what showed up as wire layers:
#1 *,#10*,#12*,#14*,#16*,#18*,#2 *,#3 *,#4 *,#5 *,#6 *,#8 *,1(0*,111*,2(0*,262*,3(0*,313*,373*,4(0*,444*,535*,646*,777*,BUS*,CAB*,DIR*,ETH*,FIB*,JUM*,SHI*,VEN*,WIRES *,_MU*,WIRES*,WIRE *,FWI*,DLO*,FDL*
The ones in red showed up on their own and were never designated as wire layers by me.
_MU* of course refers to the _MULTI_WIRE layer, which is a necessary layer for Fan In/Fan Out operations, and I can just remove it from the wire layers while leaving it as a layer.
WIRES* is apparently a redundant entry to WIRES * (I edited the WIRES layer to be named WIRES - INTERNAL and added WIRES - INTERCONNECT and WIRES - FIELD). Leaving this alone could be okay, I suppose, as there are no other layers (wire layers or otherwise) with the word WIRES in it.
The rest of them were mysteriously brought in and have no corresponding wire layers either in the template or in the drawing.
For the most part, this is a non-issue, but the Multi_Wire one is problematic. I need to figure out how to keep the _MU* from being added automatically when I create a drawing, otherwise I will have to manually remove that layer every time.
Any clue on how to figure this out?