Via stiching issues, am I using it wrong or is the stiching lacking in functionallity?

[ragnar_tollin]

It's great to see that Fusion has finally gotten a via stiching tool. It is however in my opinion somewhat unseless except for the most basic designs, unless I do not understand the tool and there's some hidden options I haven't tried/found.

Background: I have a 3 dm2 PCB with 6 layers containing USB (diff pairs), UART, GPIOs, GND planes, power plane etc. that will be EMC tested to CISPR 11 class B. I will definately want to stich it, either with the tool or manually, but since I have diff pairs, it puts restraints on the stiching. I have "large" silk screen text for part name, rev and PN for my PCB that I want to be able to route under. I have already in the design process worked through all silk screen component name placements. I do not want to redo this, but rather manually placing GND vias close to vital functions.

Issue: when performing stiching, the stiching feature does not adhere to (some?) design rules (custom keepout/signal-signal distance etc) as far as I can tell, but stiches whereever there's not a pad/via/trace conflict. I've had to amend my diff pairs to place them where they remove the vias, and polygon keep out zones where the diff pair layer change vias are. This works somewhat ok, but there seems to be no option to force the via stiching to not interfere with my component name placement since via stiching does not fully care about DR as far as I can tell. I would have wanted a specific rule section for stiching, where I can set specific distance rules for via stiching, tell it to not stich where there's text etc, alt be able to manually remove stiched vias that interfere with my design.

I do not mind manually placing GND vias close to my components since that gives me oversight and control, but as the stiching feature is working atm, it's close to useless for me. I do not undestand how it cannot respect the ruleset I have set up? Or am I missing features?

IMO, I should be able to delete individual vias in the stiching, convert stiched vias to normal vias, create via stiching keepout, or create a specific rule set for via stiching including do not sitch @ distance to specific signal & component names. Any two of those options would be acceptable.

Edit: adding a tented via option for stiched vias would also remove the entire issue since the text would then be on top of the solder mask with the via bellow. If this would be considered, I would definately need control of individually tenting top and/or bottom layer. TBH, this addition would actually be even better from a design perspective since it would save me space & work.

[jorge_garcia · Accepted solution]

Hello @ragnar_tollin,

I hope you're doing well. I have shared this thread with the developer responsible for via stitching. In this first iteration of via stitching you don't have individual control of the vias nor the ability to convert the stitch to normal vias. 

The rules should be respected though. Could you give me more details about the restricts you drew and the rules you established? Maybe something in the setup is off.

Let me know if there's anything else I can do for you.

Best Regards,

[ragnar_tollin]

Thanks, after tinkering around a bit more and seeing what the featur can and cannot do, this is rather a feature request for the via stiching. And I want to emphasise that I understand that this is the first iteration of the feature which might not accomondate my design needs, having the feature is still a major improvement in the SW.

To explain better there are two features that I am missing here:

Problem 1:

I do not want to create a clearance rule for my USB-GND since that creates a hole in my gnd planes where I do USB layer transition -> impedance change/issue for USB. Bc of this there's no way for me to create clearance between USB diff pairs and via stiching. Solutions/improvements could be:
a) Beeing able to delete individual vias
b) Move the via stiching around

c) Specific DR field for via stiching separated from signal/via DR

d) Stiching vias respecting polygon cutouts and not beening placed in cutouts would allow for selected stiching vias to be removed

Problem 2:

During the drawing process, I position component names. After performing via stiching, the stiching does not respect my DR for soldermask - silkscreen, as far as I can see. Solutions/improvements could be:

a) Include soldermask - silkscreen DR in via stiching

b) Add option for tented vias (top/bot layer selectable individually) for via stiching

c) Add possibility to delete individual vias in via stiching (preferrably option for manually adding vias to via stiching as well)

d) Possibility to move via stiching around

[jorge_garcia · Accepted solution]

Hello @ragnar_tollin ,

Thank you for these suggestions, I have passed them along to our developers for review.

In the meantime, for issue 1 you could make small via stitch polygons to stitch only the specific areas you want. I know that's more manual than what you are suggesting but just trying to give you a midterm solution. 

Let me know if there's anything else I can do for you.

Best Regards,

[chuck_toddN7PTC]

@jorge_garcia 

 One other feature that needs to be supported by via stitching function is via shielding of traces. As shown in the image below.

Thanks for what you do.

BR -Chuck

[ragnar_tollin]

I agree that this would be a usefull feature to include as well

[jorge_garcia]

Hi @chuck_toddN7PTC ,

This one is on the roadmap for phase 2 of via stitching. I don't have an ETA as to when that supposed to become available but it is in our plans to support using via stitching for shielding natively. In the meantime you can achieve this using the create drill line array ULP.

I've attached it for your convenience.

Let me know if there's anything else I can do for you.

Best Regards,

[pal.szabo]

Hi @chuck_toddN7PTC , @ragnar_tollin,

Found this old thread and just wanted to let you know (in case I haven't already in a newer thread) that there is a free and open-source add-in for Fusion that supports via stitching along signals/lines, with optional preview. It is called Electronics Extended Toolbox and it's available from the Autodesk App Store, both for Windows and Mac.

The way I use it is running it once for the board outline and once for each RF/high speed signal that needs GND fencing. Then I draw lines on an unused user layer and run via fencing for that layer to get 1D stitching patterns. It is still a bit manual work, but I have full control on where the vias will end up. It does NOT respect the rules whatsoever, but you have the preview and get the DRC errors afterwards.

Best regards,

Paul