topic Re: Restrict layers for internal copper? in Fusion Electronics Forum

Restrict layers for internal copper?

chris.eganY2EK3 — Fri, 05 May 2023 14:05:50 GMT

Are there really no restrict layers for internal copper layers? I have a part that needs a specific cutout on all layers for RF reasons and it seems crazy that I have to draw the internal restricts manually in design....

Re: Restrict layers for internal copper?

jorge_garcia — Fri, 05 May 2023 18:01:52 GMT

Hi @chris.eganY2EK3,

I hope you're doing well. It's true there are no restrict layers for the internal layers. However, you can use cutout polygons in the inner layers to create voids in the polygons.

You set the polygon type to be cutout and then draw it on the inner layer.

Let me know if there's anything else I can do for you.

Best Regards,

Re: Restrict layers for internal copper?

chris.eganY2EK3 — Fri, 05 May 2023 18:15:34 GMT

That is how I have solved the problem. But for 4+ layer boards it would be significantly more convenient to be able to draw the restricts directly into the footprint.

Re: Restrict layers for internal copper?

mtl_asm — Fri, 05 May 2023 20:11:05 GMT

+1 for restrict layers on all copper layers. especially with how the autorouter is implemented in eagle, it ignores polygons but obeys t/brestrict layer iirc (unless it has been updated in fusion).

Re: Restrict layers for internal copper?

michielcnossen — Tue, 26 Aug 2025 11:17:35 GMT

Yes please add this. You could also use it to realize clearance around unused midlayer pads, which now is too small.