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    <title>topic Thermals not rendering properly, DRC not catching violation? in Fusion Electronics Forum</title>
    <link>https://forums.autodesk.com/t5/fusion-electronics-forum/thermals-not-rendering-properly-drc-not-catching-violation/m-p/12423027#M4364</link>
    <description>&lt;P&gt;Context: In a design migrated from Eagle, I found the thermals in FE to have a different width from the EAGLE design. I realise that FE separates out the setting of the thermal width, which is a good change. During the migration, FE sets the thermal width to the same value the line width had in the respective polygon in Eagle, presumably to achieve the same thermal width. But the result is thinner than it was in Eagle. The example area is under a BGA chip (around H4 pin, named in bottom picture), with nested GND polygons (one spans the whole PCB with rank 3, the other only the BGA with rank 1).&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Eagle:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dev2EP8UX_0-1701853174221.png" style="width: 600px;"&gt;&lt;img src="https://forums.autodesk.com/t5/image/serverpage/image-id/1301372i63F4DB35DD4602F3/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dev2EP8UX_0-1701853174221.png" alt="dev2EP8UX_0-1701853174221.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;FE:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dev2EP8UX_1-1701853377478.png" style="width: 600px;"&gt;&lt;img src="https://forums.autodesk.com/t5/image/serverpage/image-id/1301377i441EB952A64DE483/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dev2EP8UX_1-1701853377478.png" alt="dev2EP8UX_1-1701853377478.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;The thermals on the H4 contact are much thinner than in the Eagle original.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Problem:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Then I manually adjusted FE's thermal width set in the BGA's GND polygon to visually match the width of the thermals in the Eagle design, i.e., I changed thermal width such that it results in thermals on H4 pin to be approximately same width as in EAGLE. The result looks a bit odd:&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dev2EP8UX_2-1701854907524.png" style="width: 600px;"&gt;&lt;img src="https://forums.autodesk.com/t5/image/serverpage/image-id/1301390iE4807FE5DC3C56B7/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dev2EP8UX_2-1701854907524.png" alt="dev2EP8UX_2-1701854907524.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;If I increase the thermal width, this continues to almost a short:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dev2EP8UX_3-1701855049088.png" style="width: 600px;"&gt;&lt;img src="https://forums.autodesk.com/t5/image/serverpage/image-id/1301391iF10433E0A4BE102F/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dev2EP8UX_3-1701855049088.png" alt="dev2EP8UX_3-1701855049088.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The DRC doesn't complain about this. To prove the DRC is working, I arbitrarily thicken a trace... this is being correctly flagged:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dev2EP8UX_4-1701855277307.png" style="width: 600px;"&gt;&lt;img src="https://forums.autodesk.com/t5/image/serverpage/image-id/1301393iFAC2007C702012A0/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dev2EP8UX_4-1701855277307.png" alt="dev2EP8UX_4-1701855277307.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Is this behaviour expected?&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Wed, 06 Dec 2023 12:24:44 GMT</pubDate>
    <dc:creator>dev2EP8UX</dc:creator>
    <dc:date>2023-12-06T12:24:44Z</dc:date>
    <item>
      <title>Thermals not rendering properly, DRC not catching violation?</title>
      <link>https://forums.autodesk.com/t5/fusion-electronics-forum/thermals-not-rendering-properly-drc-not-catching-violation/m-p/12423027#M4364</link>
      <description>&lt;P&gt;Context: In a design migrated from Eagle, I found the thermals in FE to have a different width from the EAGLE design. I realise that FE separates out the setting of the thermal width, which is a good change. During the migration, FE sets the thermal width to the same value the line width had in the respective polygon in Eagle, presumably to achieve the same thermal width. But the result is thinner than it was in Eagle. The example area is under a BGA chip (around H4 pin, named in bottom picture), with nested GND polygons (one spans the whole PCB with rank 3, the other only the BGA with rank 1).&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Eagle:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dev2EP8UX_0-1701853174221.png" style="width: 600px;"&gt;&lt;img src="https://forums.autodesk.com/t5/image/serverpage/image-id/1301372i63F4DB35DD4602F3/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dev2EP8UX_0-1701853174221.png" alt="dev2EP8UX_0-1701853174221.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;FE:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dev2EP8UX_1-1701853377478.png" style="width: 600px;"&gt;&lt;img src="https://forums.autodesk.com/t5/image/serverpage/image-id/1301377i441EB952A64DE483/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dev2EP8UX_1-1701853377478.png" alt="dev2EP8UX_1-1701853377478.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;The thermals on the H4 contact are much thinner than in the Eagle original.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Problem:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Then I manually adjusted FE's thermal width set in the BGA's GND polygon to visually match the width of the thermals in the Eagle design, i.e., I changed thermal width such that it results in thermals on H4 pin to be approximately same width as in EAGLE. The result looks a bit odd:&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dev2EP8UX_2-1701854907524.png" style="width: 600px;"&gt;&lt;img src="https://forums.autodesk.com/t5/image/serverpage/image-id/1301390iE4807FE5DC3C56B7/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dev2EP8UX_2-1701854907524.png" alt="dev2EP8UX_2-1701854907524.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;If I increase the thermal width, this continues to almost a short:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dev2EP8UX_3-1701855049088.png" style="width: 600px;"&gt;&lt;img src="https://forums.autodesk.com/t5/image/serverpage/image-id/1301391iF10433E0A4BE102F/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dev2EP8UX_3-1701855049088.png" alt="dev2EP8UX_3-1701855049088.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;The DRC doesn't complain about this. To prove the DRC is working, I arbitrarily thicken a trace... this is being correctly flagged:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="dev2EP8UX_4-1701855277307.png" style="width: 600px;"&gt;&lt;img src="https://forums.autodesk.com/t5/image/serverpage/image-id/1301393iFAC2007C702012A0/image-size/medium?v=v2&amp;amp;px=400" role="button" title="dev2EP8UX_4-1701855277307.png" alt="dev2EP8UX_4-1701855277307.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Is this behaviour expected?&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 06 Dec 2023 12:24:44 GMT</pubDate>
      <guid>https://forums.autodesk.com/t5/fusion-electronics-forum/thermals-not-rendering-properly-drc-not-catching-violation/m-p/12423027#M4364</guid>
      <dc:creator>dev2EP8UX</dc:creator>
      <dc:date>2023-12-06T12:24:44Z</dc:date>
    </item>
    <item>
      <title>Re: Thermals not rendering properly, DRC not catching violation?</title>
      <link>https://forums.autodesk.com/t5/fusion-electronics-forum/thermals-not-rendering-properly-drc-not-catching-violation/m-p/12424494#M4365</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://forums.autodesk.com/t5/user/viewprofilepage/user-id/11103067"&gt;@dev2EP8UX&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I hope you're doing well. Definitely not intended. Would you be able to send us the design or&amp;nbsp; a simplified version that reproduces the problem? With a file I can pass along to the developers it's much easier to get these things fixed.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thank you in advanced for your attention.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;/P&gt;</description>
      <pubDate>Wed, 06 Dec 2023 22:03:16 GMT</pubDate>
      <guid>https://forums.autodesk.com/t5/fusion-electronics-forum/thermals-not-rendering-properly-drc-not-catching-violation/m-p/12424494#M4365</guid>
      <dc:creator>jorge_garcia</dc:creator>
      <dc:date>2023-12-06T22:03:16Z</dc:date>
    </item>
    <item>
      <title>Re: Thermals not rendering properly, DRC not catching violation?</title>
      <link>https://forums.autodesk.com/t5/fusion-electronics-forum/thermals-not-rendering-properly-drc-not-catching-violation/m-p/12425297#M4366</link>
      <description>&lt;P&gt;Thanks. I cannot forward the whole design due to NDA. Could I save part of it as a design block... would that work? Or what is the simplest way to export a part of the design?&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 07 Dec 2023 09:06:46 GMT</pubDate>
      <guid>https://forums.autodesk.com/t5/fusion-electronics-forum/thermals-not-rendering-properly-drc-not-catching-violation/m-p/12425297#M4366</guid>
      <dc:creator>dev2EP8UX</dc:creator>
      <dc:date>2023-12-07T09:06:46Z</dc:date>
    </item>
    <item>
      <title>Re: Thermals not rendering properly, DRC not catching violation?</title>
      <link>https://forums.autodesk.com/t5/fusion-electronics-forum/thermals-not-rendering-properly-drc-not-catching-violation/m-p/12426777#M4367</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://forums.autodesk.com/t5/user/viewprofilepage/user-id/11103067"&gt;@dev2EP8UX&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I hope you're doing well. Easiest way to do this is to save a copy of the design, remove all the special sauce leaving only enough to show the issue. Then export the design as a Fusion360 archive.&lt;BR /&gt;&lt;BR /&gt;Currently, Fusion can't author designblocks so that unfortunately is not an option.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Let me know if there's anything else I can do for you.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best Regards,&lt;/P&gt;</description>
      <pubDate>Thu, 07 Dec 2023 19:57:24 GMT</pubDate>
      <guid>https://forums.autodesk.com/t5/fusion-electronics-forum/thermals-not-rendering-properly-drc-not-catching-violation/m-p/12426777#M4367</guid>
      <dc:creator>jorge_garcia</dc:creator>
      <dc:date>2023-12-07T19:57:24Z</dc:date>
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