topic Re: Issues routing large 4 layer PCB in EAGLE Forum

Issues routing large 4 layer PCB

tthoen — Fri, 09 Feb 2018 11:03:51 GMT

Hello,

I am a long time Eagle user (currently using a licensed version 7.7 Ultimate version) but have not routed a 4 layer board before. I have followed the tutorial suggestions but never get to 100%, and the program locks up after it attempts to route. The board is through hole only, 11" x 13.9". I'm not sure where to start to determine where the issue is. Does anyone have any suggestions?

Best,

T. Thoen

Re: Issues routing large 4 layer PCB

tthoen — Fri, 09 Feb 2018 18:45:24 GMT

Some more information:

No blind or buried vias, Layer setup: (1*2+3*16), two inner power layers, ground, vcc, both are solid pour polygons.

I've read some posts about doing multiple autorouting passes but haven't tried this yet.

Thank you in advance for any suggestions!

Re: Issues routing large 4 layer PCB

jorge_garcia — Fri, 09 Feb 2018 22:48:22 GMT

Hi @tthoen,

I hope you're doing well. That's a pretty large board. In the future I recommend you define your layer stackup from the outer surfaces towards the middle. So instead of (1*2+3*16) use (1*2+15*16). This falls in line with the default templates that ship with EAGLE so you wouldn't have to do anything special with the CAM processor.

It's very likely that EAGLE hasn't locked up, the TopRouter just takes a long time to run. Try this, click on the Autorouter icon and then in the setup dialog uncheck the variant with TopRouter check box and run the autorouter.

Keep in mind that there are no guarantees that the Autorouter can route a board 100% so don't let that alarm you. For your power planes you should do the multiple passes, since the autorouter can be made to do the drops to the planes.

Let me know if there's anything else I can do for you.

Best Regards,

Re: Issues routing large 4 layer PCB

tthoen — Fri, 09 Feb 2018 23:28:23 GMT

Thanks so much George,

I changed the 5V inner layer to 3 to 15 and renamed it, and re-created the polygon; however I don't know how to delete the old layer (#3).

Turning off the TopRouter seemed to help for sure.

I think I've made some progress, however I feel like there are so many variables I'm not sure what to try. I've started by just routing the top and bottom layers which works - I get to 100%; however when I start the autorouter I get a warning:

Layer 2 ($+5V), 3 (L3), 15 (DGND) used but not enabled!

Objects therein may collide with vias placed by the autorouter. Do you wish to run the autorouter anyway?"

Is this an issue?

I have tried doing the routing in passes, starting with the signal layers, now when I try routing the GND and 5V planes it gets to 100%. Before I switched to layers 1,2,15,16 I wasn't seeing any thermals from the pads to the pours - now that I switched them it seems to be working!

In the manual it says to select the largest possible line width for the polygons - what is a reasonable value?

Thanks again for the help - I think I'm getting closer!

Re: Issues routing large 4 layer PCB

tthoen — Fri, 09 Feb 2018 23:53:29 GMT

One other issue I'm running into - overall there is no interference between the ground planes and the top and bottom layers. However, if there are any square pads, or oval pads, the ground pour overlaps it. Any suggestions on what I need to change to make sure this doesn't happen?

Thanks again!

Re: Issues routing large 4 layer PCB

one-of-the-robs — Sat, 10 Feb 2018 09:50:36 GMT

@tthoen wrote:
One other issue I'm running into - overall there is no interference between the ground planes and the top and bottom layers. However, if there are any square pads, or oval pads, the ground pour overlaps it. Any suggestions on what I need to change to make sure this doesn't happen?

I may be wrong here (I'm sure Jorge will correct me if I am) but I think the pad shape doesn't apply to inner layers. The pad on the inner layers is round and (potentially) small, so the "overlap" you're seeing doesn't cause a problem. You can check this in the manufacturing tool, I think, or definitely by looking at the Gerbers it creates, or (if I've understood some other posts right - I've not tried this) by setting the pad colour to background and hiding the outer layers.

Re: Issues routing large 4 layer PCB

tthoen — Sat, 10 Feb 2018 17:13:51 GMT

Yes, that makes sense! I was concerned at first as Eagle was generating an error overlap message, but after switching the layers on and off it looks good.

I'm having the files checked with Freedfm at Advanced Circuits, but in summary I think the #1 issue was using the wrong layer numbers for the inner power planes; I think once that was changed it pretty much fixed the problem. Also doing the outer layer routing first, then the inner layers as individual steps. I'm not sure that I'm 100% out of the woods yet but will update when I find out.

Thanks so much!

Re: Issues routing large 4 layer PCB

jorge_garcia — Mon, 12 Feb 2018 20:01:21 GMT

Hi @tthoen,

I hope you're doing well. I'm glad you are making progress. I'll answer your questions in order.

1) To remove layer 3, make sure to delete any copper objects drawn on that layer you want to leave it empty. Then go to DRC > Layers tab and remove it from there. Click apply and that should get rid of it. If that doesn't work in the in the EAGLE command line type:

LAYER -3;

Which will delete the layer.

2) The error "Layer 2 ($+5V), 3 (L3), 15 (DGND) used but not enabled!" can be very important. Whenever a layer is disabled in the autoruter, the autorouter treats it as if it didn't exist. What this means is that if there is a buried via on the inner layers the Autorouter won't see it and it might create a short by placing a through hole via through a buried via. If you are not using blind and buried vias then you can safely ignore this message.

3) As far as polygon width is concerned as long as you don't use 0 you will be OK. A good starting value is the minimum width specified in the DRC of your design.

Please let me know if there's anything else I can do for you.

Best Regards,

Re: Issues routing large 4 layer PCB

tthoen — Mon, 12 Feb 2018 21:31:25 GMT

Thanks Jorge,

No blind or buried vias so I think I'm good on the warning.

I ran it through AC's DFM and it cleared, so I think I'm good!

Thanks so much for the help.

Tom